I'm designing the following function: $$F = ((A'+B) \times (A+B'))'$$ This is the schematic:
Now I know that in general PMOS width has to be 2-3 times that of NMOS width. But how do you decide exactly what width in the first place? I know there are considerations to keep in mind such as the area, rise and fall times, current etc.
Do we simply pick a value for NMOS and make PMOS 2-3+ times of that then play around with it to optimize the performance as required? If its more complicated than that, then what parameters do I need to know in order to calculate the width?