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I'm designing the following function: $$F = ((A'+B) \times (A+B'))'$$ This is the schematic:

Now I know that in general PMOS width has to be 2-3 times that of NMOS width. But how do you decide exactly what width in the first place? I know there are considerations to keep in mind such as the area, rise and fall times, current etc.

Do we simply pick a value for NMOS and make PMOS 2-3+ times of that then play around with it to optimize the performance as required? If its more complicated than that, then what parameters do I need to know in order to calculate the width?

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I think it depend on the target rise time, fall rime, power, Cload.

  1. Begin with min W and min length of NMOS and make PMOS 2-3+ times of that.

  2. Simulation with your cap. load

--> RESULT: rise time, fall time, power --> Match your target or not? After that, you can make decision for design with some of changing of device size.

  1. Sometime, logical effort method will help you make decision how many stages of your circuit. But this method will take time for calculation.

Example:

  • Block function --> connect cap. load.
  • Block function --> inverter 1x --> cap. Load
  • Block function --> inverter 1x ---> inverter 2x --> cap. Load.

Hope it help you.

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