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Suppose that we have a synchronous 4bit counter A that counts from 0 to 9 synchronized with a clock signal CP. We put an AND gate such that the signal Y = Q3*Q0 is 1 when we count a decade. The signal Y is now driven to both another counter B that counts decades and the RESET pin of counter A.

My question is the following:

Which option is better, namely a synchronous or an asynchronous counter, to use for counter B in order to count these periodic phenomena (a decade occurs always after 10 pulses)?

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It is best to use the second counter with a synchronous design and share the same clock between both counters.

Use the decoded "decade pulse" as a count enable of the second counter.

Use the decoded "decade pulse" as a synchronous load back to zero of the first counter as opposed to connecting it to an asynchronous clear input.

The reason these steps are very important is because it is possible that the output of the decade decode AND gate output could have glitches on its output as the counter outputs change state. Using that output as a clock could result in the glitches giving extra clock pulses.

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  • \$\begingroup\$ Suppose we build counter B with synchronous design using some T flip-flops. So far you have proposed me to drive Y to the input of the T flip-flop of the LSB. However is the pulse Y that is produced by Y enough to make the input go high and tick the clock once simultaneously? Or it is too short? \$\endgroup\$ – bolzano Sep 10 '16 at 12:26
  • \$\begingroup\$ The clock should ideally be a 50% duty cycle waveform derived from a source separate from the two counter circuits and then used to clock ALL the flip-flops in the the counters. Your choice to select the flop types (D, T or JK). \$\endgroup\$ – Michael Karas Sep 10 '16 at 12:33
  • \$\begingroup\$ If you use the steps I outline the "decade decode" pulse should nominally be a full clock period wide. \$\endgroup\$ – Michael Karas Sep 10 '16 at 12:35

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