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Analog Devices has published a note on high speed PCB layout, which shows examples of proper board layout for SOIC packaged op amps (figure 9, a & c). The note emphasizes that "keeping trace lengths short is paramount".

The first example routes the feedback path around the amplifier. The traces are very long, which should be avoided.

A second example routes the feedback path under the amplifier, placing the feedback resistor on the opposite side of the board. This reduces trace lengths, but requires vias. Vias "can introduce parasitic capacitance and inductance", so this should equally be avoided.

I was wondering whether it was not a better alternative to route the vias under the SOIC package (but still on the same layer) and place the feedback resistor above the op amp as shown below.

enter image description here

This way the trace lengths are kept reasonably short, without using vias.

But I guess if this was a better solution the author would have mentioned it. Is there a specific reason for not routing the feedback traces under the op amp package? Is this an acceptable, possibly even better layout for SOIC packaged op amps?

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Although vias 'can introduce parasitics', the important thing is the detail, how much extra inductance in a via compared to a length of trace?

Your idea has merit, but without a more detailed analysis of path lengths, stray inductance, stray capacitance, of both layouts, it would not be possible to declare a winner.

In addition to overall length of the feedback path (and here we dive into more detail), the capacitance on the -ve input pin is a key factor in feedback stability, usually more important than the total length. Your method has to have a track long enough to escape the package on the side, whereas a via to the other side could place Rf directly opposite the -ve input pin.

It's often not clear whether 'short track length' is being used to encourage low inductance end to end, low stray capacitance to ground, or low phase shift when viewed as a transmission line. C to ground is a killer, and that stray ground capacitance varies proportionally to the length of the track, but only very weakly as the width, shortening the track is much more effective than making it narrower.

It's interesting to note that the highest speed op-amps (GHz GBW and above) have a pair of output pins both bonded directly to the output pin on the chip, one on the 'output' side for the conventional output, and one next to the input pin, for direct connection to the feedback components. Take a look at the Analog Devices' AD8045 data sheet for instance

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  • \$\begingroup\$ So if I understand you correctly the pcb layout should actually try to minimize the capacitance between the non inverting input and ground, thus keep that trace length as short as possible. Keeping the trace of the output short is less important as the effect of C between output and ground is less severe? \$\endgroup\$ – kassiopeia Sep 13 '16 at 21:57
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    \$\begingroup\$ Yes. The output trace inductance alters the effective value of Rf, which to first order is usually unimportant. The output trace capcitance to ground is driven by the low amplifier output impedance, also usually less of a problem, except in unity gain stages when that node is effectively the -ve input as well. The capcitance to ground on the inverting input puts an extra pole into the closed loop transfer function, and causes instability. Put 'inverting input capacitance instability' into google, and read. \$\endgroup\$ – Neil_UK Sep 14 '16 at 6:19
  • \$\begingroup\$ Thanks a lot. Just another point: the article goes on by explaining how a guard ring around the inv input can help shield that (figure 15), but doesn't that add extra C to ground (in case of an inv amp for instance)? \$\endgroup\$ – kassiopeia Sep 19 '16 at 19:51
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    \$\begingroup\$ @kassiopeia 'that' in fig 15 is stray pA currents, conducted on the surface of the board, usually by moisture attracted to salts from human fingerprints, guards may increase ground C slightly. Guard tracks may look 'groundy' if driven from low pass filters, the stray C through dielectric to ground plane in usually an order of magnitude more than strays 'sideways' to adjacent tracks, like guards. It's a compromise, the stray current may wipe out sensitivity, the stray C reduces stability, and you must design for both. I picked AD8045 as an example without having read that far into your link! \$\endgroup\$ – Neil_UK Sep 20 '16 at 6:37
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keeping the loop area smallest is desired for low ESL and tracks shortest reduces capacitance w.r.t ground plane. Vias do add inductance due to aspect ratio and length but much less than a loop around the chip.

So under the chip is the shortest path, smallest loop and smallest Cf for Rf.

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    \$\begingroup\$ This just repeats what the article and theory says, without answering the particular question. \$\endgroup\$ – pipe Sep 12 '16 at 9:06

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