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Recently I have found difficulties to control clearance between Polygon and Trace/track when pouring a layer on one of our PCB. I found out that clearance is much smaller than usual. I checked the electrical clearance design rules and all unactivated them to verify that this problem was not coming from design rules but still.
Any idea where those persisting settings may be set ?
Unless things have changed recently it's set by the clearance design rules. I have no idea what happens if there is no applicable clearance rule but it wouldn't surpise me if it chooses to use a very small clearance.
I usually set a clearance rule specifically for polygons (use "inpolygon" in the query for one of the objects) to give the clearance I want arround polygons, often quite a bit higher than what I use as my regular clearance rule.
