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I have a pipelined system that outputs serial samples on port A:

b0 b1 b2 b3 b4 b5 b6 ....

On the port B I want to have this, at the same time of port A:

b1 b2 b3 b4 b5 b6...

Practically the outputs are these:

A -> b0 b1 b2 b3 b4...

B -> b1 b2 b3 b4 b5...

How can I obtain this behavior without interruptions and holes between samples? I thought to using an async dual port RAM but I'm not sure..Maybe a dual edge register? Is these some way to use just one clock?

Thank you

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    \$\begingroup\$ so you want each sample on Port B before it has been generated on port A? \$\endgroup\$ – Brian Drummond Sep 12 '16 at 20:07
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Unless I am misunderstanding something about what you're trying to build, the simplest way to do that is to add a single pipeline delay into the A path so that it's delayed by one sample with respect to the B path. No need for a dual port RAM here.

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  • \$\begingroup\$ mmm I explained bad my problem sorry.. I think is more complex. There are 2 port A and B. \$\endgroup\$ – Stefano Sep 12 '16 at 22:21
  • \$\begingroup\$ Are these b0, b1, b2, ... on port A and B coming from the same source? \$\endgroup\$ – alex.forencich Sep 12 '16 at 22:24
  • \$\begingroup\$ mmm I explained bad my problem sorry.. I think is more complex. There are 2 port A and B. Their outputs are independent, on A i have a0 a1 a2 and on B I have b0 b1 b2 etc. When on port A I have a7, on port B i want have a8 at the same time. \$\endgroup\$ – Stefano Sep 12 '16 at 22:27
  • \$\begingroup\$ Maybe you should draw a block diagram. Is this data just stored in RAM and you need to read out two different words at the same time? Is it coming from another computation or module? And do you have one set of data or two? (are the ports completely different, or is one a 'delayed' copy of the other?) \$\endgroup\$ – alex.forencich Sep 12 '16 at 22:54
  • \$\begingroup\$ The data come from 2 different blocks. There is not any memory, all pipelined. However I think to resolve with only delays. \$\endgroup\$ – Stefano Sep 12 '16 at 23:32

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