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Consider: you have a power plane on a 4-layer PCB with different power rails of different values on this power plane.

  1. How do you decide shape and sizing (border / limit) of polygon on the surface of the plane and why?

  2. Do you cover whole PCB plane with power polygon by splitting area with only power polygon or do you keep some space empty of power? Do you cover some space with ground area on this power plane? Why?

  3. What shape and position should be avoided and why (such as edges)?

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  • \$\begingroup\$ Power plane size will depend upon the IR drop encountered in plane. You can use any tool or few excel tools are also available to approximate. Shape should be such that it should cover all the pins connected to that power rail. Avoid using Power and GND pours in one plane. \$\endgroup\$ – user19579 Oct 14 '16 at 5:40
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Generally you would have large areas with splits between areas of different voltages, covering the entire PCB area. Something like this:

enter image description here

You would avoid having power planes where they could cause problems, such as near the mains or where they could couple undesirably to something sensitive.

You also pull back the power plane from the edges by some reasonable amount for the accuracy of your PCB manufacturing process, say 1mm or 0.5mm so the copper is guaranteed to be buried within the PCB. More if you are using V-groove or sheared outlines.

With most EDA programs you will be working with a negative on the power planes so you will draw tracks or keepouts to separate the areas ('split the plane') rather than to create copper polygons.

Here is another example with 5 distinct areas defined in the power plane (the one in the centre is selected):

enter image description here

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  • \$\begingroup\$ so based on your answer, considering a power plane the full pcb should be filled with only net related to power. There is no ground surrounding power rails in power plane. Am I correct ? 2./ I would like to know in which case we should not pour in some area. \$\endgroup\$ – chris Sep 14 '16 at 1:45
  • \$\begingroup\$ I think you're right. A 4 layer design usually means 1 full plane is power and 1 full plane is ground. \$\endgroup\$ – Jim Sep 14 '16 at 2:27
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There is a fairly subtle gotcha with 4 layer stackups in that you usually have some signal traces on L4, and these tend to be referenced (in terms of return currents) to the power plane. If these traces have fast edges and cross splits in the power plane you can end up with an EMC or SI fail due to the increased loop areas (I had a 40MHz SPI bus do that to me, very annoying).

For this reason the shape of copper pours on L3 should be carefully considered in combination with the tracking on L4 and the placement of decoupling caps between L2 & L3 (A Decoupling cap or so near every location that a trace changes reference pour is a good thing and will minimise HF loop areas.

Sometimes a mixed layer (Polygons + tracks) can actually be better...

Personally if I am going to split the power plane extensively, and if I have fast edge rates in play that cannot be kept on L1 I tend to reach for a 6 layer with ground on 2 & 5 and lots of stitching vias, but my industry is not so cost sensitive that the difference between 4 and 6 layers matters.

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