There is a fairly subtle gotcha with 4 layer stackups in that you usually have some signal traces on L4, and these tend to be referenced (in terms of return currents) to the power plane. If these traces have fast edges and cross splits in the power plane you can end up with an EMC or SI fail due to the increased loop areas (I had a 40MHz SPI bus do that to me, very annoying).
For this reason the shape of copper pours on L3 should be carefully considered in combination with the tracking on L4 and the placement of decoupling caps between L2 & L3 (A Decoupling cap or so near every location that a trace changes reference pour is a good thing and will minimise HF loop areas.
Sometimes a mixed layer (Polygons + tracks) can actually be better...
Personally if I am going to split the power plane extensively, and if I have fast edge rates in play that cannot be kept on L1 I tend to reach for a 6 layer with ground on 2 & 5 and lots of stitching vias, but my industry is not so cost sensitive that the difference between 4 and 6 layers matters.