Working with the FPGA section of the Zynq chip of the Zedboard. I want to use an external signal as clock (in any case, the tool infers that it is a clock since I have @(posedge sclk_loopback) in the HDL).
From the forums, I see that I need to use "clock capable pins", and the JA4 and JA10 are the two available "clock capable" pins in the PMOD connectors. However, I get this error:
[Place 30-876] Port 'sclk_loopback' is assigned to PACKAGE_PIN 'AA8' which can only be used as the N side of a differential clock input.
I can't seem to find the necessary information to follow through. It looks like JA4 would be the positive input and JA10 the negative --- if so, do they have to be complementary signals? or would it work if I tie JA10 to GND and then feed a clock signal through JA4?
Any pointers will be much appreciated.
Note: the circuit does work if I override the DRC check as suggested at the end of the error message (set_property CLOCK_DEDICATED_ROUTE FALSE...). But it does not work reliably at the speed that I need it to work, so I suspect my next step is to fix this external clock issue.