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Working with the FPGA section of the Zynq chip of the Zedboard. I want to use an external signal as clock (in any case, the tool infers that it is a clock since I have @(posedge sclk_loopback) in the HDL).

From the forums, I see that I need to use "clock capable pins", and the JA4 and JA10 are the two available "clock capable" pins in the PMOD connectors. However, I get this error:

[Place 30-876] Port 'sclk_loopback' is assigned to PACKAGE_PIN 'AA8' which can only be used as the N side of a differential clock input.

I can't seem to find the necessary information to follow through. It looks like JA4 would be the positive input and JA10 the negative --- if so, do they have to be complementary signals? or would it work if I tie JA10 to GND and then feed a clock signal through JA4?

Any pointers will be much appreciated.

Note: the circuit does work if I override the DRC check as suggested at the end of the error message (set_property CLOCK_DEDICATED_ROUTE FALSE...). But it does not work reliably at the speed that I need it to work, so I suspect my next step is to fix this external clock issue.

Thanks!

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I don't know that particular board, but there is more then you ever want to know about the clocking on the 7 series parts here:

http://www.xilinx.com/support/documentation/user_guides/ug472_7Series_Clocking.pdf

Basically you can run a single ended clock into the thing (Subject to picking an appropriate IO standard), but there are constraints to watch out for if you wish to clock multiple regions from one input. Single ended clocks (Not usually a good idea at high speed!) must go in on the positive half of the pair (You can use the negative pin as a general IO pin if using a single ended IO standard).

For a global clock you want a pin with MRCC (Multi region clock capable) in the name Vivado pin planner is useful here for figuring out what can do what.

73

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  • \$\begingroup\$ In case it makes a difference: it's not a global/system clock signal; I'm generating a signal that will be the SCLK of an external device through an SPI-like interface, and I need to use that same SCLK to clock a shift register to deserialize what the external device sends (and only for that). To avoid issues with signals skew, I output the SCLK through one JA pin, and connect it (externally) to another JA pin that I use as a "looopback" input for the SCLK. As I understand, I can simply use JA4 for sclk_loopback and ignore JA10? \$\endgroup\$ – Cal-linux Sep 15 '16 at 13:04
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    \$\begingroup\$ You might want to look at the IDELAY and possibly ODELAY primitives, possibly together with the possibilities inherent in the ISERDES and OSERDES blocks. What you are doing should work, but it seems like doing things the hard way. \$\endgroup\$ – Dan Mills Sep 15 '16 at 16:35

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