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So I've been doing some reseach on DTL ( Diode Transistor Logic ) and started doing some problems, but the problem i stumbled onto gives me some headache. enter image description here

The actual problem given is

Given a DTL circuit on the image, determine the logic function of the circuit and the minimal value of resistance \$R_{Cmax}\$ in the collector area of transistor so that the output transistor is saturated. Known parameters : \$\beta_{min}=50\$,\$\beta=100\$, \$V_{CC}=5V\$, \$V_{BET}=0.5V\$, \$V_{BES}=0.7V\$, \$V_{BE}=V_D=0.6V\$, \$V_{CES}=0.2V\$

The data given is vague , so i assume

  • \$V_{BES}\$ - base-emitter voltage of the transistors in saturation mode
  • \$V_{BE}\$ - base-emitter voltage of the transistors
  • \$V_D\$ - voltage drop across the diodes
  • \$ V_{CES} \$ - collector emitter voltage in saturation

As for the logic circuit, i cant make any sensible logic function out it. I also can't see the purpose of the diode between the two transistors. As for the calculations themselves, i remove the input diodes and try to solve the circuit. The circuit itself doesn't seem too difficult, but I'm not sure what is the required resistance. Also, what is the purpose of \$\beta_{min}\$ here?

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    \$\begingroup\$ You really can't see the logic function if you draw a truth-table? 3 inputs gives you 8 possibilities, so work out the output for each one. \$\endgroup\$ – brhans Sep 13 '16 at 21:08
  • \$\begingroup\$ @brhans Well, like i said, not understanding the circuit completely is kind of a problem. I'm assuming the first transistor will saturate for all low inputs, and the second one will be cut off. But I'm not quite sure that's true :) If i understood the circuit completely, I'd be able to determine the function \$\endgroup\$ – Transcendental Sep 13 '16 at 21:11
  • \$\begingroup\$ Why would the 1st transistor saturate with all inputs low? Its a NPN and needs a positive Vbe before it turns on. \$\endgroup\$ – brhans Sep 13 '16 at 21:12
  • \$\begingroup\$ My bad, I mean to say when all inputs are high ( hence, all diodes reverse biased ), the transistor will saturate. If any diode is low, the current will flow trough the diode, and the transistor will be off. \$\endgroup\$ – Transcendental Sep 13 '16 at 21:16
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    \$\begingroup\$ @brhans Well, if that was correct, then, when the first transistor is in saturation, the voltage across the 5k ohm resistor will cause the second transistor to saturate as well, hence the output is a 0. Similarly, when the first transistor is cut off, then the second one will be as well. This seems like NAND. \$\endgroup\$ – Transcendental Sep 13 '16 at 21:38
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Look at the following two schematics. On the left is where none of the inputs are present, or else they are all high and their diodes aren't conducting. On the right is where one or more of the input diodes are conducting. I've provided some voltages and currents to look at, and an explanation about why \$R_1\$ is present, as well.

I've taken the time here to re-arrange the schematic a little bit. The central reason is that I wanted to lay out the four diodes in a way that may help you see what is happening and why \$D_1\$ is there. The reason will become clear when we look at the right schematic (its not important for the left one.)

schematic

simulate this circuit – Schematic created using CircuitLab

On the left, none of the input diodes are conducting. So the base of \$Q_1\$ is pulled up and will require a tiny base current (and therefore a tiny voltage drop across \$R_4\$.) The voltage at the base of \$Q_1\$ is figured out by working upward from the emitter of \$Q_2\$, which is at \$0V\$. Since both BJTs are on (just follow the path from \$R_3\$ and to \$R_4\$, through the base-emitter of \$Q_1\$, through \$D_1\$, and then through the base-emitter of \$Q_2\$) the base of \$Q_2\$ will be pulled up to about \$750mV\$ or so. \$D_1\$ will add another \$700mV\$ or so. Then \$Q_2\$'s base-emitter adds another .. maybe \$700mV\$ to that. I got about \$2.15V\$, but it will actually probably be a little less than that, as I over estimated the voltages by a small bit.) This means that about \$1.6mA\$ will be rushing through \$R_3\$, almost all of which must go through the collector of \$Q_1\$. The tiny base current needed for \$Q_1\$ will leave a tiny voltage drop across \$R_4\$. But not much.

All this means is that \$Q_2\$ will be driven into hard saturation with about \$1.6mA\$ into its base-emitter. The output will be able to sink up to about 10-20 times that much. Which means it can sink a lot. It may need to, as you will soon see (as to why) in the right schematic.

In the right schematic, one or more of the diodes are pulled "down." Their voltage value at the cathode end will be near zero, but I've allowed for some hundreds of millivolts there and called it "LO." So the the anode of these diodes will be pulled down close to ground. This means that \$R_3\$ and \$R_4\$ now form a divider and will need to sink about \$1mA\$ into those diodes.

(Which is why I mentioned that the left schematic may need to sink a fair amount of current. If each circuit driven low by the left schematic needs to sink \$1mA\$, then driving 5 inputs would need to sink \$5mA\$, etc. It adds up fast.)

Now in the right schematic, you can see that with the base of \$Q_1\$ set to perhaps as much as \$1V\$, it would be possible for \$Q_2\$'s base to be at some halfway-point between \$1V\$ and \$0V\$. If there were \$500mV\$ each, let's say, then both of the transistors might still be ON. This would NOT be good. So \$D_1\$ is inserted there to make SURE to soak up enough voltage to ensure that the combined base-emitter junctions of \$Q_1\$ and \$Q_2\$ can't see much remaining voltage to share. Far, far too little to do any damage, anyway.

Suppose there still is a very tiny current there. Just as a what-if. Well, this tiny current will present a very tiny drop across \$R_1\$ and therefore the base of \$Q_2\$ will still be practically at \$0V\$ and solidly OFF. Even if \$Q_1\$ is still just slightly conducting, it won't turn on \$Q_2\$. So, in effect, \$Q_1\$ and \$Q_2\$ will both be OFF and this allows \$R_2\$ to pull up the output to \$V_{CC}\$.

The right circuit cannot source much current, as \$R_2\$ is all there is for that. But luckily, when diodes are all OFF, they don't need much. So that works okay, too.

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  • \$\begingroup\$ And why R4 is connected with Q1's collector instead with VCC? \$\endgroup\$ – Circuit fantasist Aug 18 '17 at 13:37
  • \$\begingroup\$ @Circuitfantasist I can't tell what you are suggesting. If \$R_4\$ is connected to \$V_{CC}\$, what is the collector of \Q_1\$ then connected to? Perhaps you should write up a question and arrange the circuit (and do some analysis) in the way you want, and then point me to your question. I'll try and answer it, if you do. \$\endgroup\$ – jonk Aug 18 '17 at 14:52
  • \$\begingroup\$ @Jonk, my assumption is that initially R4 has been connected between the base and VCC (acting as a base resistor) and R3 - between the Q1's collector and VCC (acting as a collector resistor). Then, for some reason, the circuit has been modified - R4 has been disconnected from VCC and connected to the common point between Q1's collector and the lower end of R3. My question is, "Why?" \$\endgroup\$ – Circuit fantasist Aug 18 '17 at 19:50
  • \$\begingroup\$ @Circuitfantasist Ah. I think I see what you want. Just a second. \$\endgroup\$ – jonk Aug 18 '17 at 20:03
  • \$\begingroup\$ @Circuitfantasist Running things this way establishes an approximately 'constant' current through \$R_3\$ and either diverts that current either: (1) to the collector to make the output an active low; or, (2) into a sinking input, releasing the output to be pulled high by \$R_2\$. Does that help? Note also that the collector voltage doesn't vary that much. \$\endgroup\$ – jonk Aug 18 '17 at 20:07
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I will try to do something not so usual for this forum - to reveal the basic idea, the philosophy behind this class of BJT logic gates (DTL and TTL) instead to analyze specific circuit details. Figuratively speaking, I will try "to show the forest for the trees":)

IMO the main idea in all these implementations is to divert the current flowing through a diode element by connecting in parallel another diode element with lower threshold voltage. The benefit of this current "self-commutation" (redirection, diverting or steering), is the rapid transition since: first, the current is switched very sharply; second, the voltage across the parallel-connected elements almost does not change (stray capacitances are not recharged). You can observe this circuit trick in an attractive way by connecting a 1.5V red LED in parallel to a 2.5V green LED.

In the classic DTL circuit, the high-threshold diode "element" is implemented by connecting in series three diode elements - two diodes and one base-emitter junction, having a total voltage threshold of 3 x 0.7V = 2.1V. When at least one of the input diodes (VF = 0.7V) connects in parallel to this diode network, it diverts all the network current through itself.

In the modified DTL gate, discussed here, one of the diodes is replaced by the base-emitter junction of another transistor (Q1). As a result, the input currents (drawn through D2 - D4) can be small, and the base current driving Q2 can be big.

But in the circuit solution, shown in the question, there is an odd connection - the Q1's base resistor of 2k is connected to the Q1's collector instead to VCC as we would expect. Why?

IMO in this way, a parallel negative feedback is introduced (like in the case of the input part of the simple current mirror). As a result, when all the input voltages are high (logical "1"), and the input diodes are cut-off, the Q1's collector-emitter voltage will be never smaller than 0.7V... Q1 will never saturate... and will rapidly cut-off when at least one input becomes "0" (small base charge)...

When at least one input becomes "0"... Does this not remind you of OR function?

The paradox here is that really the input diodes are connected in parallel to each other (and to the last part of the gate) what is typical for the OR diode gate. But they are inverted thus implementing an AND logic function (according to de Morgan's laws). I have thoroughly considered this trick in the ResearchGate question below:

What is the basic idea of the input logical part of TTL, DTL and DL gates?

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  • \$\begingroup\$ I've found this circuit in the web - 930 Series DTL (ca 1964). \$\endgroup\$ – Circuit fantasist Aug 21 '17 at 14:35

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