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What are the software tools used in the industry to build bit-accurate models for algorithms (algorithms which are to be implemented in FPGAs)?


Before using a tool like Quartus, we tried our algorithm in C language. It worked. But the problem is floating point arithmetic is utilized in C. But when we have to implement it in FPGA we only have fixed point arithmetic. So before coding in verilog, are there any tools to convert the earlier mentioned C code to a bit-accurate model which uses fixed point arithmetic instead of floating point arithmetic!!! What are the tools used in industry if such tools exist?

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    \$\begingroup\$ Question is a bit vague, but usually you use the FPGA vendor's synthesis tools (Quartus / Vivado). \$\endgroup\$ – pjc50 Sep 14 '16 at 9:12
  • \$\begingroup\$ Problem: switching from floating to fixed will probably give you bit-different results. There's no automated solution for this. Are you actually looking for a "cycle accurate" simulation which you'll verify the Verilog against? Or C-to-Verilog (which seldom works well)? \$\endgroup\$ – pjc50 Sep 14 '16 at 9:55
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    \$\begingroup\$ The first step is to write another implementation in C, using integer operations only (scaling them as needed to represent fixed-point values). Write a test framework that verifies that the results of both implementations (floating-point and integer) are numerically "close enough" -- whatever that means in your application. Then use the integer C implementation as the model against which you verify the RTL implementaiton. \$\endgroup\$ – Dave Tweed Sep 14 '16 at 11:04
  • \$\begingroup\$ Modelsim and simulink come in handy with fixed point simulations. \$\endgroup\$ – Voltage Spike Sep 14 '16 at 15:18
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Not an industry standard, but one personal view : my technique is to model the algorithm with a generic package, which I can instantiate with floating point or any fixed point types I want.

The floating point algorithm comes from C or Fortran or whatever - after rewriting as a generic, I instantiate it with floating point types and verify its outputs match the original.

Then I can instantiate the same code with any size of fixed point, and verify its accuracy meets my needs - modifying the fixed point types (adding higher resolution ones for intermediate results, etc) as necessary.

Translating it into VHDL code is usually trivial; adapting it further (e.g. pipelining it for synthesis) somewhat less so, but at every stage I have a high level bit-accurate fixed point model sa a reference, so I can track any deviation from that.

This assumes you have a language that supports fixed point and floating point types nicely, and allows generic packages and subprograms (like template classes in C++).

My choice for this (and most general purpose, i.e. non-hardware programming) is Ada-2005 or 2012.

Its ease of interfacing with C or other languages makes re-using high level models easy, and its similarity to VHDL makes translation to VHDL relatively pain free (though VHDL only supports fixed point types via libraries). Proper fixed point support is much less painful than faking it using integer types, even in a language that lets you define integers of any size you want, rather than the restricted set available in C etc.

As far as I know, System C aims to provide facilities to allow a similar approach, though via add-on libraries rather than inherently in the language. Maybe someone else will comment on how well that works. I can't, as I've never had occasion to use it.

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  • \$\begingroup\$ Thank you very much for the detailed answer! :) It is really useful! @Brian Drummond \$\endgroup\$ – RONEY Sep 15 '16 at 8:16
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I have done this using Matlab - prototyping/developing my algorithm in base Matlab, and then integerising it using Matlab's toolboxes.

I write my Matlab to be as little like the intended VHDL as possible, so that I have a very different mindset whilst writing it - a long way from RTL. The advantage of this is that I catch more bugs. If I write "RTL" Matlab and then use a more mechanical translation to RTL HDL, I find I include the same bug in both "sides".

I write out verification vectors from the Matlab model (as .vhd files with VHDL arrays in them) and my testbench can then verify that my VHDL implementation is bit-accurate with the Matlab prototype.

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