I am wondering if there are generally accepted methods of estimating the power consumption of digital operations as they are implemented in custom logic (ASIC). From this previous questions, it seems that people have done it with simulator tools once the RTL is written.
What I am looking for, however, is a back-of-the-evelope method along the lines of this previous question. Perhaps this is an attempt at taking the question a bit further. In my case I am interested to see if there is a way to estimate a modular operation by itself.
For example when calculating the mean of
n 8-bit numbers I would like to say that the power cost of such an operation would be:
P_mean8 = n*P_add8 + P_divide8
I realize that:
- Placement and routing (fanout, etc.) will play an important role in the final power number but I am not interested in getting bogged down in the details of such. I am more interested in getting a rough estimate assuming reasonably good practices.
- Technology nodes (90nm vs. 12nm) will change the number but I am hoping there is a method that will take a few parameters from the technology node and scale the answer accordingly