I have a GPIO driving a logic inverter which is then connected to the input of an NPN Darlington pair IC (ULN2803). The MCU and inverter are powered by the same 3v3 rail.

I am seeing behaviour which I did not expect at the output of the Darlington pair, even when the output is not connected to anything. I have observed this behaviour in LTSpice (when I approximately modelled the ULN2803 internals) and on my physical circuit (by probing with a CRO). The simulation is shown below.

When the input to the Darlington pair is logic low, the output is (as expected) basically 0V. However, when the input is logic high, the floating output of the Darlington pair appears to read ~630mV.

I'm struggling to understand this observation - any insights would be appreciated (even if it means pointing out some aspect of my stupidity :-) ) Thanks!

LTSpice simulation Green Trace = output of V1

Blue Trace = Collector of Q1 & Q2

  • \$\begingroup\$ Without a pullup on the collector, what were you expecting? Consider : Q1 base is 2 diode drops above 0V, and Q1 base-collector junction is forward biased... \$\endgroup\$ – Brian Drummond Sep 16 '16 at 10:03
  • \$\begingroup\$ Quite right @Brian. I was forgetting about the base-collector diode. In reality this is only a snippet of a larger design but I got curious when I saw this effect while troubleshooting something else... \$\endgroup\$ – MrWhippy Sep 16 '16 at 11:49

A ULN2803 is usually used to drive a load of some sort connected between the output (the collectors of Q1 and Q2) and a higher voltage, typically 12V. Without a load the output will not behave as you expect. However, what you expected to happen is not what really happens.

With the input off (or 0V) transistors Q1 and Q2 will be off, and the output will "float". With a pullup resistor connected between the output and 12V the output will be pulled up to 12V. With the input on (3.3V) Q1 and Q2 will turn on and pull the output down to near 0V.

If you do not have a load or pull-up resistor on the output then when you apply 3.3V to the input the base of Q1 will be clamped to around 1.2V due to the two forward biased base-emitter diodes in Q1 followed by Q2. The base-collector diode in Q1 will also be forward biased, so the 1.2v on the base of Q1 appears on the collector of Q1, minus another 0.6V diode drop. Hence you see approx 0.6V on the collector.

  • \$\begingroup\$ Thanks for your helpful answer @Steve. I understood that the base of Q1 would see 2x base-emitter diode drops but I was forgetting about the base-collector diode! Thanks again. \$\endgroup\$ – MrWhippy Sep 16 '16 at 11:47

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