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i'm currently working on a PCB for an 8x8x8 LED cube. The PCB layout in the current status you can find below:

Data transfer interface

The ATmega328P (16Mhz) will use SPI to send the needed data to four TLC5940 chips (12bit grey scale, 16 channel LED driver) and one TPIC6B595 (8 bit shift register). In order to get high enough FPS and still have enough CPU time for effects the SPI interface needs to run at 8 MHz.

I'm a little bit unsure about the correct layout to avoid problems like corrupted data.

Relevant layout parts for this questions:

A) SPI Data: From the ATmega SPI pin to the first TLC and then daisy chained via the next three TLCs to the TPIC (every trace ~2-3cm long)

B) SPI Clock: From the ATmega SPI Clock pin in two directions. Firstly to the corresponding ISP header and secondly under all the TLCs to the TPIC. Every TLC data clock pin is connected by a very short branch of the clock line. The line ends in the clock pin of the TPIC chip. (total line length ~23-25cm long without branches)

C) GS Clock: Needed to keep the grey scale PWM of the TLCs going. Via the set CKOUT fuse a constant 8Mhz signal is send via this line to all TLC greyscale clock pins (~20cm long without branches).

D) Blank: From ATmega to all TLCs, ending in the last one. Usually GND level, toggled regularly to reset PWM counter in TLCs. During data update for the TLCs it is high for the first few transmitted bytes and then set low again while the rest of the bytes is shifted out (to reduce LED downtime)

E) Latch: From ATmega connected to all TLCs and the TPIC chip. Always low except for a quick toggle (when SPI is not active)

F) PCB Layers: Red lines top, blue lines bottom. The bottom has additionally a complete ground fill, as seen in the magnification of one TLC:

TLC close up

My questions regarding the data transmission layout:

1) Is it ok to route those lines over ~14cm in parallel? Blank und latch ("calm lines") are in the middle and the "noisy" lines GS Clock and SPI clock on the outside (0.05 inch distance between each line), but therefore close to IC pins.

2) Are the short 90° branches ok to connect every IC to the data lines or will this create problems?

3) What about signal reflection/termination (for SPI and GS clock)? I've read several articles about that topic but did not really understand all of it. Some people claim that at 8Mhz there is no problem. Others differentiate between trance length and so on. Some solutions like end line termination apparently are only working for a single load, therefore this will not work for me obviously. So far I haven't found anything concrete/clear regarding this topic. I feel like this could be a dealbreaker for my board at the moment.

4) What about the signal return path? I tried to make it possible for the return current to follow the relevant top trace on the bottom layer, but a few obstacles remain (like the connections of the GS clock, latch and blank traces to the PLC pins). Is the layout in this respect still ok?

Best regards,

ratuso

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    \$\begingroup\$ That's a nice looking layout. Judging purely by the layout, I don't think you'll have any problems with 8MHz SPI, your clearances look good and the overall design is neat and consistent. SPI is fairly resistant (in my experience) to self-induced interference. You've put a lot of thought into this by the look of it. BTW, you can save yourself a via (see pin 12 on IC3). \$\endgroup\$ – Wossname Sep 16 '16 at 12:55
  • \$\begingroup\$ Random unrelated observation: your vertical dimension annotation on the left side of the picture is not lined up with your board outline properly. \$\endgroup\$ – Wossname Sep 16 '16 at 13:19
  • \$\begingroup\$ Agreed with @Wossname. You can confidently prototype this, given the timings involved and your layout. Your worries would be justified for a x10 frequency increase. \$\endgroup\$ – dim Sep 16 '16 at 13:41
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This answer (Are termination resistors needed for UART, I2C and SPI?) basically tells you that a 50 MHz SPI is probably good for >7 cm tracks. All you have to do is keep clock and data roughly of equal length. Uni-directional SPI is quite forgiving due to the dual nature of clocking data out on one edge then clocking it back in on the other.

At 8 MHz the period is 125 ns and the time given for data to settle (following it changing on a clock edge) is therefore 62 ns. You would have to make data and SCL line lengths massively different to get anywhere near 60 nano seconds in delay.

This answer only applies to sending data out from a master - another greater problem arises when clocking data back in from a slave - this determines the maximum length of track/wire ulitimately but if you are only sending data from master to slave then no problem.

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  • \$\begingroup\$ The time to settle I get but from what I understood problems with reflection and missing termination can lead to spikes on signal edges. In this case I assume that those spike could be recognized as additional clock ticks if big enough, right? So even if the signal as settled instead of one clock tick the IC could seed multiple. Is this understanding correct? And could it be an issue here? \$\endgroup\$ – ratuso Sep 17 '16 at 15:12
  • \$\begingroup\$ Read my answer in the linked question - any questions please raise as a comment under that answer (more relevant way of doing things I reckon). \$\endgroup\$ – Andy aka Sep 17 '16 at 15:14
  • \$\begingroup\$ @ratuso, it is highly unlikely that your circuit is capable of ringing hard enough to produce spurious clock edges. It will work fine. You are not pushing the technology anywhere near to it's limits :) \$\endgroup\$ – Wossname Sep 17 '16 at 16:09

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