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Could anyone help me a bit sort this out?

I have implemented the following schematic on a PCB for the decoupling of a supply rail of an Ethernet Switch.

Schematic

More specifically it is the IO supply of the SSMII interface. This implementation is also what the manufacturer proposes. The 3.3V comes from a step-down DC-DC converter.

I have noticed that the power supply after the L (so IC side) is not very clean. When measured with the oscilloscope on pin 1 of L462, I had the following waveform

Measurement of the filtered 3.3V supply

The frequency measured by the oscilloscope is not always the same. It varies a bit between 25MHz and 60MHz. Although this was true before making the following changes (the measurement was taken with These)

  • Substitute one 10nF and one 100nF with two 330pF capacitors
  • Add an additional 4.7uF capacitor (all ceramic) at the L462.1 pin.

On the other side, the L462.2 side, all Looks quieter.

What can I additionally do in order to have a cleaner power supply? Use an additional capacitor? Replace with another value? Normally at these frequencies the 100nF and 10nF are indeed effective, no?

Here also the layout. The supply rail after the bead (the relative big component upper left) is coloured with yellow. They are all connected through a small plane on an inner layer. It is probably not ideal that many capacitors share the same via, but at this area there are not any more GND balls. Also probably the light green capacitors should be turned horizontally and be connected to the two GND vias on the right side of the image.

Layout

So, I took some new measurements by using the technique of soldering a Coax cable directly on a capacitor and the results can be seen in the waveforms below.

First at L462.1:

Measurement of the filtered 3.3V with a coax cable

and second at the L462.2 pin:

Measurement of the 3.3V at L462.2 pin with a coax cable

I mean, apart from the frequency (here I detected more clearly the 31.25MHz, which is the half of the 62.5MHz with which the data signals of this Interface work), it is still clear that the disturbances are there and that they are filtered away from the main board's supply with the ferrite bead.

Then, lastly, I substituted the ferrite bead with a 0-Ohm resistor:

Measurement of the unfiltered 3.3V with a 0-Ohm resistor instead of the bead

I think it is clear that the disturbances come from the IC and that without the filtering the situation would be worse.

So the question remains, how to make the power supply quieter?

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  • \$\begingroup\$ How do you measure it? What's your probe setup? What's the PCB layout look like? Do you have anything running at 25-60 MHz? Also, is there any capatitor behind the inductor? \$\endgroup\$ – winny Sep 16 '16 at 12:55
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    \$\begingroup\$ That 120ohm 100MHz marking is unusual for an inductor, usually an inductor would be measured in henries (milli or micro). Ohms at a frequency sounds more like a ferrite bead. These generally have a well behaved inductance up to 1MHz or so, and then go lossy, which is what is required for good EMI attenuation. But they might have less inductance than you expect. \$\endgroup\$ – Neil_UK Sep 16 '16 at 13:02
  • \$\begingroup\$ @Neil_UK This is indeed a ferrite bead and not an inductor \$\endgroup\$ – nickagian Sep 16 '16 at 13:04
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    \$\begingroup\$ @winny: As you can see, I have updated the post with the new measurements. I think it is proven that the L is indeed needed and that my first measurements were more or less correct... \$\endgroup\$ – nickagian Sep 17 '16 at 15:12
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    \$\begingroup\$ Excellent! Go to Michael Karas comment below but also try to increase the inductance and/or even more decoupling with lower ESR. If your current consumption is really low you also have the option to use a resistor in series instead of an inductor which would really put a damper in that. But again, only if the current consumption is low enough to give reasonably high values of R without dropping too much voltage. \$\endgroup\$ – winny Sep 17 '16 at 15:38
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When decoupling the use of parallel capacitors with values that are decade apart is like playing russian roulette. That is because you will get a resonant spike when the network with the bigger capacitor has become inductive and the network with smaller capacitor is still capacitive. I don't know if this is the problem here but maybe you should try replacing all the capacitors with one value either 10 or 100n. I did fast ltspice simulation to illustrate my point. Impedance with different capacitor values This is impedance with two different value capacitors connected by traces with identical inductances.

enter image description here And this is impedance with identical capacitor values.

Edit: Here is the simulation file as requested in comments:

Version 4 SHEET 1 880 680 WIRE 208 208 -16 208 WIRE 304 208 208 208 WIRE 208 240 208 208 WIRE 304 240 304 208 WIRE -16 336 -16 208 WIRE 208 336 208 304 WIRE 304 336 304 304 WIRE -16 480 -16 416 WIRE 16 480 -16 480 WIRE 208 480 208 416 WIRE 208 480 16 480 WIRE 304 480 304 416 WIRE 304 480 208 480 WIRE 16 544 16 480 FLAG 16 544 0 SYMBOL voltage -16 320 R0 SYMATTR InstName V1 SYMATTR Value "" SYMATTR Value2 AC 1 0 SYMBOL cap 192 240 R0 SYMATTR InstName C1 SYMATTR Value 100n SYMBOL ind 192 320 R0 SYMATTR InstName L1 SYMATTR Value 3.5n SYMBOL cap 288 240 R0 SYMATTR InstName C2 SYMATTR Value 10n SYMBOL ind 288 320 R0 SYMATTR InstName L2 SYMATTR Value 3.5n TEXT 432 256 Left 2 !.ac dec 1000 1 1000000000

The expression to plot is:V(n001)/I(V1).

Also I might not have understood correctly how you connected the capacitors but since inductance has a big influence here you should make sure that all the parallel caps are not connected through common but separate inductances. The motivation is that when connected in parallel the combined impedance of capacitance increases while the combined impedance of inductance reduces. So multiple capacitors having current flow through the same via is bad idea for decoupling purposes. Do whatever you can to avoid that.

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  • \$\begingroup\$ This is interesting. May I suggest that you paste in the LTSpice .ASC file and the text for your plot formula so that the OP can experiment with values typical to his PCB. A trace inductance calculator can be seen here: daycounter.com/Calculators/Microstrip-Inductor-Calculator.phtml A 15 mil wide microstrip that is 200 mils long and 20 mils above it's GND plane will have an ~3nH inductance. OP will have to decide if your example of 15nH is applicable to their layout or not. \$\endgroup\$ – Michael Karas Sep 17 '16 at 21:33
  • \$\begingroup\$ No problem but how should I include the .asc file? Also you are right about the fact that my value for inductance was a bit exaggerated which is a pity since the resonant frequency is 1/sqrt(LC) so lowering the inductance would shift it towards the problem frequency here which makes it even more prominent candidate as a solution. \$\endgroup\$ – Trafi Sep 18 '16 at 7:04
  • \$\begingroup\$ @Trafi Just open the .asc file with a text editor and copy-paste the contents here (as code, to avoid wrapping). \$\endgroup\$ – a concerned citizen Sep 18 '16 at 9:57
  • \$\begingroup\$ @Trafi - Just as said above. The LTSpice .asc file is an ordinary text file. For the OP or any other person interested in experimenting with this they can then simply cut/paste the text from this web page to a file with .asc extension and then it can simply be opened with LTSpice. \$\endgroup\$ – Michael Karas Sep 18 '16 at 10:08
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Probing and grounding setup for measurements like this make all the difference. What you are seeing on the scope may in fact be quite different from reality.

So when making the measurements make sure that the probe tip is right at the capacitor / ferrite bead node and that the probe ground is right at the IC / capacitor GND. Long test leads can pickup noise from other parts of your system. As a minimum try winding the scope GND lead around the probe body so it does not expose itself as an open antenna loop.

Also evaluate your layout so to make sure that the capacitor grounds shown return / connect directly back to the GND pins of the IC directly associated with the AA13 -> AA18 power rail pins.

Using the above careful measurement technique check if the noise that you see is indeed worse on the IC chip side of the ferrite bead. If it is then it is highly likely that layout of your PC board has less than optimum power and ground connections to the IC chip and the associated bypass capacitors. Hopefully you have a full GND plane on the board.

If the noise turns out to actually be worse on the 3.3V side of the ferrite bead then the source of the noise is most likely from the DC-DC converter that produces the 3.3V. In this case it may be helpful to add a second ferrite bead in series with the one you have now and then add an additional capacitor from between then to the GND. (This will not be of much help of course if the overall GND system on the board is compromised).

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  • \$\begingroup\$ MichaelKaras's caution about ground planes is well-considered. Those spikes are very fast, so consider also the inductance between each of those bypass capacitors on the supply side. Those inductances cause multiple resonances, especially where capacitor values are different. Physical re-placement can make a difference here. \$\endgroup\$ – glen_geek Sep 16 '16 at 13:38
  • \$\begingroup\$ @glen_geek Do you have then any proposal how? So you mean really inductance between these capacitors? How can you avoid such resonances? \$\endgroup\$ – nickagian Sep 16 '16 at 14:23
  • \$\begingroup\$ @nickagian - This is a "whack-a-mole" problem: quell one resonance, and another pops up. Broad ground and supply planes help. Or enter a black-hole:**bypass_filter_design.pdf** \$\endgroup\$ – glen_geek Sep 16 '16 at 15:09
  • \$\begingroup\$ Could you please elaborate on the paragraph "Using the above...on the board"? I mean, I have measured the power indeed as you say and I believe it is confirmed that the noise is indeed worse on the IC side. What do you mean that the PCB doesn't have optimum power and GND connections? How could I improve it? The GND is indeed common for the whole PCB. Full on layers 1, 4 and 8. Can't it just be that I need a different combination of decoupling capacitors? Or more of them? \$\endgroup\$ – nickagian Sep 17 '16 at 15:18
  • \$\begingroup\$ I cannot design your board for you over the internet but can suggest some things that can lead to more optimal power connectivity in a PC board. 1) Trying to have direct copper connections between the IC pins and the bypass capacitors. 2) Absolutely minimize the length of copper runs from IC pins to caps. 3) Minimize number of VIAs in chip to cap connections down to zero if at all possible. 4) Try to select IC chips that have their PwrPins and GndPins assigned in such a way that you can connect caps in line with 1->3 above. (continued) \$\endgroup\$ – Michael Karas Sep 17 '16 at 15:29

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