I saw the following somewhere and I'm trying to make the following with NPN transistors but I'm having some trouble.


simulate this circuit – Schematic created using CircuitLab

I want to make a circuit where, when I apply a voltage to input1, output turns on, feeding back into input2, so that input1 and 2 are both on. And when I remove voltage from input1, input2 stays on thus output stays on.

And I did it like this:


simulate this circuit

So SW1 is input 1. D3 is output. If I remove the wire connecting node x to node y, my circuit functions as an OR gate. To make the circuit above I keep SW2 open at all times. When I close SW1, I hoped D1, D2 and D3 would turn on, but only D1 and D3 turned on. So naturally, when I opened SW1, D3 turned off, which is not what I want. I tried this in falstad and it didn't work either.

So my question is: how can I correct my circuit so that it does what I want it to do (as I described above)?

I made an edit to the diagram. I removed SW2. D1 and D2 don't have a role other than to light up when the transistors are up.

Second edit: I fixed the direction of D3 and rearranged the way the circuit was feeding back into Q2.


  • 1
    \$\begingroup\$ Why not just use an OR gate? \$\endgroup\$
    – Andy aka
    Sep 16 '16 at 16:31
  • 1
    \$\begingroup\$ I'm doing it for educational purposes. Anyhow, what I'm trying to do is get SW1 to turn on D1, which in turn gets D3, but also give feedback to Q2 via node y, turning on D2. This way, when I open SW1, Q2 is still being fed and so D2 and D3 are still on, even though D1 is not on. I'm ignoring SW2, which I included in the diagram only because I made an OR gate first, then this. \$\endgroup\$ Sep 16 '16 at 17:24
  • \$\begingroup\$ But, how do you turn it off? Once you switch this one time the output will go high and prevent the input 1 from doing ANYTHING... (referring to your logic diagram not the transistor level schematic, which is quite a mess) \$\endgroup\$
    – jbord39
    Sep 16 '16 at 17:53
  • \$\begingroup\$ I'm not planning on it shutting off. It's just something I'm trying to make to satisfy myself that these things work the way I've learned. I guess I'd have to literally disconnect the voltage source (or some other component) to get D3 to turn off. \$\endgroup\$ Sep 16 '16 at 18:17
  • \$\begingroup\$ @Jozurcrunch: Okay. Once you have exhausted this line of inquiry you should read about "latches". They do a similar function but are much more general. One that could work well for this situation is an S-R latch. It can be toggled and will stay in the state forever. But there are two inputs, one to reset as well. \$\endgroup\$
    – jbord39
    Sep 16 '16 at 18:23

There are a number of problems with your circuit.

  1. You have a 1 V power source. This will not turn on an LED, never mind two in series.
  2. Assuming that's a mistake and you have about 5 V supply (based on R5 and R7 being 100 Ω and a current of 10 mA) then when you close SW2 you will put 5 V across D3 and destroy it.
  3. It's not clear what purpose D1 and D2 serve.
  4. You have wired Q1 and Q2 as voltage followers. Logic circuits would normally use some kind of common emitter.


simulate this circuit – Schematic created using CircuitLab

Figure 1. A NOR and a NOT will do the job.

  • Q1 and Q2 form a NOR gate. Turning either on will pull the common collector to ground. Note that the transistors will be driven into saturation so they could be within 0.2 V of ground whereas your arrangement could at the very best get to about 0.7 V below supply.
  • When Q1 is turned in it will turn on Q3. Its collector will be pulled high. This will turn on Q2 and latch.


simulate this circuit

Figure 2. Minimalist version.


simulate this circuit

Figure 3. Analysis of your circuit. Note that there is 0 V to bias Q2. It can't turn on.

How can I get the base voltage higher than the emitter?

You can't. That's why logic gates aren't designed that way.

  • \$\begingroup\$ You might note that the minimalist version is close to being an SCR made with complementary transistors. I would suggest a E-B resistor on either Q1 or Q2 to make it a little less sensitive (somewhere around 10K-100K). \$\endgroup\$ Sep 16 '16 at 17:42
  • \$\begingroup\$ Yes, the thyristor had crossed my mind. They used to be popular for the power-supply over-voltage crowbar circuit! \$\endgroup\$
    – Transistor
    Sep 16 '16 at 17:46
  • \$\begingroup\$ I made a change to the diagram in my question. Can you help me understand why it doesn't work? I'm really a novice and trying to get some hands on experience. I don't know why when SW1 is on, it doesn't turn on Q2. \$\endgroup\$ Sep 16 '16 at 18:20
  • \$\begingroup\$ (1) Other than removing SW2 and fixing the battery voltage you haven't changed the logic of your diagram. You've just made it harder to read by rotating D4. Let current flow from top to bottom as I edited it and not right to left. (2) To get your Q2 to turn on you have to raise the base voltage higher than the emitter voltage. You have it lower. Again, if you draw your schematic with current flow from to bottom this will be easier to spot as voltage (or potential) decreases from top to bottom of your schematic. \$\endgroup\$
    – Transistor
    Sep 16 '16 at 19:04
  • \$\begingroup\$ I removed D1 and D2, and I changed the direction of D3. I also made an adjustment to the way the output was feeding into Q2. Is this basically the first edit you did on my diagram? How can I get the base voltage higher than the emitter? \$\endgroup\$ Sep 16 '16 at 19:52

Transistor's answer is correct, but I'm adding another answer, since that answer helped me understand things in another way that might be helpful (and my comment was too long to add as a comment).

In particular:

  1. You have wired Q1 and Q2 as voltage followers. Logic circuits would normally use some kind of common emitter.

I think this helped me understand things better. As I understand it, voltage followers means that both the input and output "share" the collector (i.e. a direct connection to +5V) in the non-inverting OR gate. Each time current "falls" down the base-emitter junction, we lose 0.7 volts of signal (our "1" looks that much more like a "0"), and we can never get it back with non-inverting gates.

For example, even if we use another transistor wired as a buffer, this will only amplify current, and not voltage, because the emitter voltage needs to be lower than the base voltage to turn that transistor on. But inverting gates (common emitter) can amplify the voltage while inverting it, in a way "recharging" the signal so it can propagate indefinitely in downstream logic circuitry. I.e. even though the signal is inverted, the voltage difference between a "1" and a "0" is larger again, because we can "start fresh" from the +5V.

Another way of thinking about it is to imagine the path of a "hole", i.e. as unit of positive charge flows through your circuit. If you consider the input (the base) of Q2, and the output (the emitter) of Q2, which is wired to feedback in your original circuit, consider what your original expectation implies. It would mean that this "hole" would travel in a loop:

  • Through R3 to the base of Q2
  • Through Q2 to the emitter of Q2
  • Through R7 to R3

Alternatively, if you want to think of the path of electrons, they'd have to be making this perpetual journey in the opposite direction. Since current will only flow from a point of relatively higher voltage to a point of relatively lower voltage, this cannot work in this way.


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