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Actually it is nothing to do with Ethernet specific, but just to be accurate, I have several SS-SMII Interface signals between an FPGA and a Switch. The interface has 8 data signals, one synchronization signal and a 125MHz clock for each direction. Due to EMC reasons I have inserted 22 Ohm series resistors on the transmitter side of each of the signals.

Unfortunately the board is still not compliant with the required CE Standards for radiated emissions and I am right now trying to improve it further. I have the feeling (after excluding other potential sources of radiation) that the problem lies with these signals.

One possibility I would like to explore is that of the signal integrity of the signals. For this reason I took some measurements with an active probe, making sure the ground loop is minimized.

Now for some wavforms. First a TXCLK signal from the Switch to the FPGA.

Right at the ball of the Switch (transmitter):

TXCLK @ Switch

and then at the ball of the FPGA (receiver):

TXCLK @ FPGA

Then an RXCLK signal from the FPGA to the Switch.

At the ball of the FPGA (transmitter):

RXCLK @ FPGA

and at the ball of the switch (receiver):

RXCLK @ Switch

The problem is I don't have the experience to evaluate the measurements myself...!

Some of my thoughts:

  1. Is it normal that all the signals (or at least the mesurements show so) go down until around -400mV? I suppose not, right? What can I do to improve that?
  2. The same as point 1. but for the upper part of the signals. They go up until around 4V (it clearly is a 3.3V Interface).
  3. Is it normal that at the transmitter side of the TXCLK (see the first image above) the Signal looks so bad? What could be the reason for that?
  4. Do I need a termination on the receiver side? Is it acceptable to put both a series resistor and a receiver side termination? I have only seen one of them but not both at the same time.
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    \$\begingroup\$ Just to be "accurate", you need to specify which FPGA you are using, how its I/O are configured in terms of controlled impedance, and what is "a Switch" and its I/O impedances, and what is the impedance and length of interface traces. Also, a stand-alone board cannot be compliant or non-compliant, only the entire device, with case and all shields, can be a subject of regulations. \$\endgroup\$ – Ale..chenski Sep 17 '16 at 16:38
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    \$\begingroup\$ Schematic and layouts would be more helpful than scope traces. If you want to talk about the scope traces, we need to know what kind of probe you're using and where you're connecting the ground. A photo of the probe and how you're connecting it to the board would be the best way to present that information. \$\endgroup\$ – The Photon Sep 17 '16 at 16:49
  • \$\begingroup\$ For accurate measurements of this sort the probe's "ground loop" should be not just "minimized", but completely ELIMINATED. A fully differential probe would be the best. \$\endgroup\$ – Ale..chenski Sep 17 '16 at 17:17
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As I can deduct from Picture #1, the design has the interface trace length of about 10 cm (about 600ps one way flight time), and the trace impedance is quite higher than the impedance of driver. For unterminated transmission lines the transmitter-side "shoulder" is normal, but it should be half way (Rdriver = Rtline) for the best signal integrity.

The overshoot and undershoot on signals is likely caused by bad probe connection to ground.

You may want to increase values of serial resistors and see if it improves waveforms, although they do not look bad at all already.

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Let's look at an ideal case, a zero impedance transmitter driving a series termination resistor with matching impedance into a not terminated transmission line. At the transmitter with the initial voltage step, the series resistor and the transmission line form a voltage divider. Half of the voltage step goes on the transmission line.

The half voltage step travels to the high impedance end of the transmission line. There is a 100% reflection, doubling the half voltage step to the originally driven level.

The reflected half voltage step travels back to the transmitter. Since the series resistor matches the transmission line impedance. The step is "absorbed".

Similar mechanism applies in your case except that the impedance at the transmitter is lower than the line. So the initial voltage step is higher than 1/2 and the voltage after reflection is high than the driven voltage. Of course, that does not account for all the effects that are different from the idealized case.

By the way, series termination is problematic when there are receivers not at the end of the line. Only at the end of line that the intermediate voltage step, which can be in between thresholds, is not seen.

Also, try switching the series resistors to ferrite beads. With ferrite beads, some trial and error may be needed.

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