I'm not a huge expert on hardware verification, I mean I know what the purpose of verification is (basically check if the system what it is expected to do) and I've used some tools for verification, usually I design an equivalent in Software using C/C++ language and than I compare somehow the VHDL/Verilog equivalent against this.

However it seems like most of this tools are not free, I was wondering if it is possible to use some very simple verification technique from scratch. Most of this tools as far as I know they use first order logic to after analyzing both Software and HDL code. Is there some very simple approach (other than exhaustive simulation) that could easily implement by him self to check the equivalency?

Maybe there's some very simple algorithm that can be easily used, and I'm not aware of.


  • \$\begingroup\$ And how do you verify that your Software equivalent is equivalent to anything? \$\endgroup\$ – Ale..chenski Sep 17 '16 at 18:35
  • \$\begingroup\$ Assuming the software version is correct, I have to verify hardware is equivalent to software. To most stupid example that I can come up with is the equivalence I/O, i assume to provide the same input for both sw and hw and I want to verify that the output is also the same. \$\endgroup\$ – user8469759 Sep 17 '16 at 18:58

Verification is a huge field. Just like in software there are many levels of verification e.g. code coverage, path coverage etc. It all depends on the application. Blinking LED: check the frequency in simulation; the control system that keeps your turbofan below its melting point: you better test the hell out of it.

We can split verification into two main categories: functional and formal. Your tool chain usually comes with functional verification capabilities i.e. you put something at the input and you check the output. Say you are designing an adder. What you can do is create a test bench, put each possible combination at the input, and compare the output. This is what I needed to do recently for a Kogge-Stone adder I was designing for an FPGA.

If you spend some money you can buy tools that can do code coverage, path coverage etc. You can actually do that with some open source tools too. If you spend a lot of money, you can get a formal verification tool, which proves that your design is equivalent to the specification. This can be really important in some fields.

I would suggest to start looking at test benches, if you have not done verification before. This will give you a good introduction to functional verification.

  • \$\begingroup\$ I am not sure about the statement that "toilchain come with functional verification". In my experience toolchains come with nothing. You have to create your own test benches to verify something. Unless you bought some IP, which usually comes with comprehensive verification suite, frequently amounting to 95% of the entire IP code. Still +1. \$\endgroup\$ – Ale..chenski Sep 17 '16 at 19:15
  • \$\begingroup\$ @AliChen I mean they come with simulation. They are capable of completing functional verification when provided with a test bench. For formal verification you actually need additional tools. Edited the answer for clarity. \$\endgroup\$ – user110971 Sep 17 '16 at 19:17

If I understand the question correctly, you need to convert your software C/C++ model into a verification test bench, using System Verilog, C# or something. It could be even straightforward. Then you need to hook up this testbench model to hardware HDL in your HDL design environment. To get it somewhat automated and avoid visual compare of waveform, your test bench can/should include variety of logical checks of your I/O vectors in critical points of time. Usually this process takes 90% of design time, and no tools can do this job for you, simple or complex.

  • \$\begingroup\$ I'm not sure that I'm understanding your answer. Take as example a 32 bit adder, in C/C++ the model would be just a function... In hardware I could want to implement a carry look ahead adder maybe. However an adder is an adder so the relationship input output doesn't change. So, again for example, I could want to verify that for each input pair given to both HDL and C the resulting output is the same. Are saying in this case you would use the C Model to build a proper test bench for verification? \$\endgroup\$ – user8469759 Sep 17 '16 at 20:36
  • \$\begingroup\$ An adder is not just "an adder". Adders can be pipelined for speed, or can be implemented in microcode, so the output can be delayed, and the "software" must know when it is acceptable to check for output. Hardware is not limited to "input-output relationship". In most cases the hardware is awfully complicated finite state machines that sequentially generate enormous amount of signal combinations, all of which must be validated. That's why a test bench could be more complicated than the hardware itself. \$\endgroup\$ – Ale..chenski Sep 18 '16 at 0:33

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