I am in the process of designing a lab power supply for myself as a learning opportunity. However, I have hit a road block in my design. I am trying to use a single Vishay IRF520 mosfet as a DIY linear regulator for both current and voltage regulation. I can't find any LDO regulators that are single-pin adjustable down to nearly 0V other than the Linear Technologies LT3083, but the LT3083 has a few gotchas in its maximum ratings--particularly on input voltage. Hence, a DIY regulator.
The why is in the specs of my supply design and in the architecture:
- Single rail supply for test load
- Linear regulation of both current and voltage
- Output voltage adjustable from 0V (or as close as possible) to 20V
- Current limit adjustable from 0A (or as close as possible) to 2A
- Microcontroller control
Here's a breakdown of the current power supply architecture:
- Voltage follower architecture using 4-switch buck-boost switch-mode pre-regulator
- Voltage output is 2V-22V @ 2.5A max current
- This 22V max from the pre-regulator exceeds the 18V max input on the LT3083 if the output is shorted to ground
- Input and output voltage and current sensed using operational amplifiers
- Voltage sensors use a simple non-inverting voltage-follower off a 1/10 resistor divider
- Current sensors use differential amplifiers with a gain of 5 across 200mΩ shunt resistors
- All direct sensing and control of switch-mode supply and linear regulator is handled by the μC via ADC, DAC, and ePot on I²C bus
- Op amps are powered via the same 12V supply as the smps pre-regulator to ensure stable op amp operation
Parts not shown in the attached screenshot that play a role:
- Microcontroller: Atmel ATMega328P (familiarity with Arduinos influenced this choice)
- DAC: Maxim MAX5815
- 12-bit, 4-channel DAC
- Configured to use 4.096V internal ref, connected to ref pin of ADC
- Controls I_SET and V_SET
- ADC: Texas Instruments ADC128D818 (12-bit, 8-channel ADC)
- Receives VIN_SENSE, IIN_SENSE, ILIM_SENSE, IOUT_SENSE, and VOUT_SENSE
To explain what should be going on at each of the op amps, from left to right (voltage sensors not pictured):
- VCC coming in from the top left ranges from 2V to 22V at up to 2.2A maximum off the SMPS pre-regulator and passes through the 200mΩ shunt, which translates into a 0V-440mV drop across the shunt that's amplified by the differential amp (Amp 1) with a gain of 5 to 0V-2.2V
- IIN_SENSE, output of Amp 1, feeds into the ADC and to the non-inverting input of the current limiter (Amp 2, a unity gain differential amp). I_SET, a 0V-4.096V signal from the DAC, feeds into the inverting input of Amp 2. I_SET is subtracted from IIN_SENSE, and Amp 2 output (ILIM_SENSE) stays locked at 0V until IIN_SENSE rises above I_SET (and enters current limiting mode). When ILIM_SENSE rises above 0V, the ADC's interrupt pin is triggered which alerts the μC that current limiting mode is active and to actively monitor IOUT_SENSE to ensure it stays constant.
- ILIM_SENSE feeds into the ADC and into the inverting input of the voltage limiter (Amp 3). The non-inverting input of Amp 3 receives the V_SET signal (also 0V-4.096V) from the DAC. ILIM_SENSE is subtracted from V_SET to pull it down when ILIM_SENSE rises above 0V. When ILIM_SENSE is 0V, Amp 3 output tracks with V_SET.
- Amp 3 output feeds into non-inverting input of linear regulator (Amp 4). Inverting input of Amp 4 is fed by a 1/10 voltage divider off the output of Q_REG (IRF520 MOSFET), and the output of Amp 4 feeds into the gate of Q_REG to regulate both voltage and current simultaneously.
- Amp 5 is a separate current sensor, identical in design to Amp 1, that feeds back into the ADC. The microcontroller uses the feedback from all four sensors sensors to adjust I_SET and V_SET accordingly as the electrical characteristics of the shunt resistors and Q_REG change while a load is connected to the power supply, to ensure constant and stable voltage and current regulation.
At least, that's how I think it's supposed to work. I'm second-guessing all of this, and I need a sanity check. I'm trying to avoid using another IRF520 (in order to avoid introducing another RDS on the rail), but after examining the VDS vs. ID chart on the IRF520 data sheet (fig. 1, page 3), I have a feeling that pulling the regulator's output voltage down to also regulate current isn't going to work simply because the output voltage and current of my project stays well within the saturation region of the mosfet.
I've already looked up designs for using an op amp and a mosfet as a constant current source, and if I absolutely need a second mosfet on the high side of Q_REG as a current regulator, I could use the output of Amp 5 as the sense resistor. But I want to avoid using a second mosfet if possible.
I haven't tested any of this design, yet. I don't have my workbench set up and I also do not have a sufficient power supply to use for testing.
Any input here would be greatly appreciated.