# Analog-Digital converter's LSB formula

What is the correct definition of the LSB voltage for an analog to digital converter?

I have found two formulas:

LSB = FS / (2N)

LSB = FS / (2N - 1)

N ... resolution in bits of the ADC.

FS ... Full scale input range

Has this anything to do with the location of the first code transition?

Can someone clarify this problem for me?

The definition for the LSB as $$LSB = \frac{FSR}{2^N}$$ can be found in the IEEE Standard 1241-2010 ("IEEE Standard for Terminology and Test Methods for Analog-to-Digital Converters") and is commonly used for commercial devices. It can therefore be considered the right definition.

For integrated circuit design, when building an ADC as part of a signal processing chain or as a sub-block of a larger ADC it sometimes can make sense to to define the LSB differently ($LSB = FSR/(2^N-1)$).

The reason is that there are two conventions for ADCs depending on the code transition levels used. One is the so-called mid-tread convention where FSR/2 is right in the middle of a code and the first transition occurs at LSB/2. The other is the mid-riser convention where FSR/2 occurs at transition and the first transition occurs at LSB.

The transfer functions of both types are shown below, the dotted lines indicate the range for mid-tread type and the dashed lines are for the mid-riser.

As shown in the graph the last-transition for the mid-tread type occurs 3/2 LSB below FSR while the first transition is at 1/2 LSB. In order to have a symmetric transfer function, the last transition is sometimes made 1/2 LSB below the maximum voltage. So one LSB is removed from the upper end.

In this case the LSB would indeed be FSR/(2^N-1).

The equation $\mathrm{LSB} = \frac{\mathrm{FS}}{2^N - 1}$ is commonly repeated, but is not in fact correct. For an ADC with $N$ bit resolution, each bit must therefore represent a span of $\frac{1}{2^N}$ of the input range. As such the equation $\mathrm{LSB} = \frac{\mathrm{FS}}{2^N}$ is correct.

So the first input will span from $\left[0 \space \frac{1}{2^N}\right)$, the second $\left[\frac{1}{2^N}\space\frac{2}{2^N}\right)$, and so fourth.

What this means is that the voltage you are measuring could be anywhere within that range, so you must decide how you want to represent it - for example you could floor and pick the bottom of the range (1), ceil and pick the top of the range (2), or pick the mid value (3). That would give calculations of:

\begin{align}\\ V_{in} &= \frac{V_{ref}\times \mathrm{Code}}{2^N}\tag1\\\\ V_{in} &= \frac{V_{ref}\times (\mathrm{Code}+1)}{2^N}\tag2\\\\ V_{in} &= \frac{V_{ref}\times (\mathrm{Code}+0.5)}{2^N}\tag3\\ \end{align}

To add a real example to the mix, take the ADC of the ATMega1284. If you refer to page 253 of the datasheet, the equation relating voltage to ADC code is given. Rearranging that into your form, it is:

$$V_{in} = \frac{V_{ref}\times \mathrm{Code}}{2^N}$$

This depends on what exactly the input voltage mapping for each digital code is, but generally the resolution (input voltage step size for incremental readings) is FS / 2N.

Consider a ideal 2-bit A/D with 0-1 input voltage range:

Input V  Output code
-------  -----------

1.0  -----
|
0.9
|      11
0.8
|   -----
0.7
|
0.6     10
|
0.5  -----
|
0.4
|      01
0.3
|   -----
0.2
|
0.1     00
|
0.0  -----

Each code represents a range of 0.25 V on the input.

• ... and step M corresponds to a measured voltage of U = FS/2^N * M + FS/2^(N+1) +- FS/2^(N+1) Sep 18, 2016 at 12:28