Could someone explain how PWM capture mode employs the Timer's Master-Slave mechanism? The example sets up input capture on Channel 2 but does not explain how IC1 is configured implicitly to capture the falling edge.
I am especially interested in these three SPL functions:
/* Select the TIM3 Input Trigger: TI2FP2 */ TIM_SelectInputTrigger(TIM3, TIM_TS_TI2FP2); /* Select the slave Mode: Reset Mode */ TIM_SelectSlaveMode(TIM3, TIM_SlaveMode_Reset); /* Enable the Master/Slave Mode */ TIM_SelectMasterSlaveMode(TIM3, TIM_MasterSlaveMode_Enable);
implemented in stm32f10x_tim.c. They all write to TIMx->SMCR.
According the diagram from UM0008 rev 14 (rev 16) ...
... TI2FP2 is not even connected to IC1, that would be TI2FP1. So I can understand that these commands configure the reset. But what causes IC1 to capture?