Consider we have two n-bit counters CNT_A and CNT_B two n-bit unsigned comparators CMP_A, CMP_B and two n-bit binary numbers N1, N2. The counters have two inputs C, L for synchronous count and load respectively such that:
- when C=L=0 counter holds its current value
- when C=1, L=0 the counter increases by 1
- when C=0 L=1 the counter synchronously load an nbit number given by the user to its input line INPUT
- when C=L=1 the counter decreases by 1
The counters also include an asynchronous reset pin RESET (the counters reset to 0 when RESET=1) and an asynchronous ENABLE pin that either enables (ENABLE=1) or disables the counter (ENABLE=0).
Consider we want to build the following digital circuit:
- CNT_1 counts from 0 to N1 (0 to N1 clock pulses)
- CNT_2 counts from 0 to N2 (N1 + 1 to N1 + N2 clock pulses)
and this process is repeated again and again.
Let x be the
== output of CMP_A and y be the
== output of CMP_B. Note that the comparators are connected to their respective counters CNT_A, CNT_B. Let Q(t) denote the state of the controller FF at time t.
For instance, consider the following two implementations:
Set ENABLE <= 1 and RESET <= 0 and use the synchronous inputs L,C to implement the counters.
Set L = 0, ENABLE <= 1 and use the asynchronous pin RESET to reset the counters.
When designing ASM charts for each implementation I came across this observation:
Asynchronous pins (case 2) ought to be of Moore type (RESET pins have values Q(t) and Q'(t) for the two counters) while the L pins (case 2) must be of Mealy Type. Besides this, the synchronous pins L1,L2,C1,C2 ought to be of Mealy Type in case 1.
Is my assumption true, namely asynchronous pins must be implemented as Moore outputs, and synchronous as Mealy ones?