Consider we have two n-bit counters CNT_A and CNT_B two n-bit unsigned comparators CMP_A, CMP_B and two n-bit binary numbers N1, N2. The counters have two inputs C, L for synchronous count and load respectively such that:

  1. when C=L=0 counter holds its current value
  2. when C=1, L=0 the counter increases by 1
  3. when C=0 L=1 the counter synchronously load an nbit number given by the user to its input line INPUT
  4. when C=L=1 the counter decreases by 1

The counters also include an asynchronous reset pin RESET (the counters reset to 0 when RESET=1) and an asynchronous ENABLE pin that either enables (ENABLE=1) or disables the counter (ENABLE=0).

Consider we want to build the following digital circuit:

  1. CNT_1 counts from 0 to N1 (0 to N1 clock pulses)
  2. CNT_2 counts from 0 to N2 (N1 + 1 to N1 + N2 clock pulses)

and this process is repeated again and again.

Let x be the == output of CMP_A and y be the == output of CMP_B. Note that the comparators are connected to their respective counters CNT_A, CNT_B. Let Q(t) denote the state of the controller FF at time t.

For instance, consider the following two implementations:

  1. Set ENABLE <= 1 and RESET <= 0 and use the synchronous inputs L,C to implement the counters.

  2. Set L = 0, ENABLE <= 1 and use the asynchronous pin RESET to reset the counters.

When designing ASM charts for each implementation I came across this observation:

Asynchronous pins (case 2) ought to be of Moore type (RESET pins have values Q(t) and Q'(t) for the two counters) while the L pins (case 2) must be of Mealy Type. Besides this, the synchronous pins L1,L2,C1,C2 ought to be of Mealy Type in case 1.

Is my assumption true, namely asynchronous pins must be implemented as Moore outputs, and synchronous as Mealy ones?


Your conclusions are not true.

The bottom line is all inputs that can cause a state change must meet setup and hold time for the next state to be definitive.

Take your example of the synchronous L pin being fed by the output of a Mealy machine. If the output of the Mealy machine violates the setup or hold time of the L pin. Then there is no guarantee which bits would perform a load and which bits would not perform a load on the particular clock edge.

It is also possible to have the output of a Mealy machine to never violate the setup and hold time. For example, if the inputs to the Mealy machine that affects a particular output is from synchronous sources, then the output is also synchronous (with some additional delay). Of course, there must be enough budget to handle the propagation delays. But that is true here and practically everywhere.


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