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I know that a simple CPU (like Intel or AMD) can consume 45-140 W and that many CPUs operate at 1.2 V, 1.25 V, etc.

So, assuming a CPU operating at 1.25 V and having TDP of 80 W... it uses 64 Amps (a lot of amps).

  1. Why does a CPU need more than 1 A in their circuit (assuming FinFET transistors)? I know that most of the time the CPU is idling, and the 60 A are all "pulses" because the CPU has a clock, but why can't a CPU operate at 1 V and 1 A?

  2. A small and fast FinFET transistor, for example: 14 nm operating at 3.0 GHz needs how many amps (approximately)?

  3. Does higher current make transistors switch on and/or off more quickly?

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    \$\begingroup\$ Modern CPUs (none of which are 'simple') require multiple voltage rails all with their own power requirements. Your question makes many assumptions and has many erroneous statements. You must consider all power requirements and not just those for a single rail. \$\endgroup\$ – Wossname Sep 19 '16 at 20:01
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    \$\begingroup\$ Do a FinFET transistor count on a modern CPU. Not every FET conducts current from Vdd to ground, but even so, 64 A gets distributed over *a very large number * of these switching FETs. \$\endgroup\$ – glen_geek Sep 19 '16 at 20:02
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    \$\begingroup\$ @EricLippert "it would have to be pulling 64 amps out of the wall" - I have a suspicion that the CPU would not be operating on 110 V. \$\endgroup\$ – Andrew Morton Sep 20 '16 at 12:10
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    \$\begingroup\$ The conserved quantity is energy, and on average also power. If a CPU draws 64 Watt, then the power supply must draw at least 64 Watt from the socket. That's <1A even at 110V. \$\endgroup\$ – MSalters Sep 20 '16 at 12:45
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    \$\begingroup\$ @EricLippert The motherboard in your computer contains a multiphase DC to DC converter that steps the supply voltage (12V in the case of a desktop, probably 12-19V in the case of a laptop) down to the core supply voltage. This is done with constant POWER, so the output current ends up being 10-20 times the input current. Not to mention the 12V supply in a desktop computer also comes from a switching power supply which also converts with constant power. The CPU in your computer probably has at least 100 power and ground pins to handle the current. \$\endgroup\$ – alex.forencich Sep 20 '16 at 13:49
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  1. CPUs are not 'simple' by any stretch of the imagination. Because they have a few billion transistors, each one of which will have some small leakage at idle and has to charge and discharge gate and interconnect capacitance in other transistors when switching. Yes, each one draws a small current, but when you multiply that by the number of transistors, you end up with a surprisingly large number. 64A is an average current already...when switching, the transistors can draw a lot more than the average, and this is smoothed out by bypass capacitors. Remember that your 64A figure came from working backwards from the TDP, making that really 64A RMS, and there can be significant variation around that at many time scales (variation during a clock cycle, variation during different operations, variation between sleep states, etc.). Also, you might be able to get away with running a CPU designed to operate at 3 GHz on 1.2 volts and 64 amps at 1 volt and 1 amp....just maybe at 3 MHz. Although at that point you then have to worry about whether the chip uses dynamic logic that has a minimum clock frequency, so maybe you would have to run it at a few hundred MHz to a GHz and cycle it into deep sleep periodically to get the average current down. The bottom line is that power = performance. The performance of most modern CPUs is actually thermally limited.
  2. This is relatively easy to calculate - \$I = C v \alpha f\$, where \$I\$ is the current, \$C\$ is the load capacitance, \$v\$ is the voltage, \$\alpha\$ is the activity factor, and \$f\$ is the switching frequency. I'll see if I can get ballpark numbers for a FinFET's gate capacitance and edit.
  3. Sort of. The faster the gate capacitance is charged or discharged, the faster the transistor will switch. Charging faster requires either a smaller capacitance (determined by geometry) or a larger current (determined by interconnect resistance and supply voltage). Individual transistors switching faster then means they can switch more often, which results in more average current draw (proportional to clock frequency).

Edit: so, http://www.synopsys.com/community/universityprogram/documents/article-iitk/25nmtriplegatefinfetswithraisedsourcedrain.pdf has a figure for the gate capacitance of a 25nm FinFET. I'm just going to call it 0.1 fF for the sake of keeping things simple. Apparently it varies with bias voltage and it will certainly vary with transistor size (transistors are sized according to their purpose in the circuit, not all of the transistors will be the same size! Larger transistors are 'stronger' as they can switch more current, but they also have higher gate capacitance and require more current to drive).

Plugging in 1.25 volts, 0.1 fF, 3 GHz, and \$\alpha = 1\$, the result is \$0.375 \mu A\$. Multiply that by 1 billion and you get 375 A. That's the required average gate current (charge per second into the gate capacitance) to switch 1 billion of these transistors at 3 GHz. That doesn't count 'shoot through,' which will occur during switching in CMOS logic. It's also an average, so the instantaneous current could vary a lot - think of how the current draw asymptotically decreases as an RC circuit charges up. Bypass capacitors on the substrate, package, and circuit board with smooth out this variation. Obviously this is just a ballpark figure, but it seems to be the right order of magnitude. This also does not consider leakage current or charge stored in other parasitics (i.e. wiring).

In most devices, \$\alpha\$ will be much less than 1 as many of the transistors will be idle on each clock cycle. This will vary depending on the function of the transistors. For example, transistors in the clock distribution network will have \$\alpha = 1\$ as they switch twice on every clock cycle. For something like a binary counter, the LSB would have \$\alpha\$ of 0.5 as it switches once per clock cycle, the next bit would have \$\alpha = 0.25\$ as it switches half as often, etc. However, for something like a cache memory, \$\alpha\$ could be very small. Take a 1 MB cache, for example. A 1 MB cache memory built with 6T SRAM cells has 48 million transistors just to store the data. It will have more for the read and write logic, demultiplexers, etc. However, only a handful would ever switch on a given clock cycle. Let's say the cache line is 128 bytes, and a new line is written on every cycle. That's 1024 bits. Assuming the cell contents and the new data are both random, 512 bits are expected to be flipped. That's 3072 transistors out of 48 million, or \$\alpha = 0.000061\$. Note that this is only for the memory array itself; the support circuitry (decoders, read/write logic, sense amps, etc.) will have a much larger \$\alpha\$. Hence why cache memory power consumption is usually dominated by leakage current - that is a LOT of idle transistors just sitting around leaking instead of switching.

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    \$\begingroup\$ 1V 1A isn't a weird target, ARM CPU's are quite commonly specc'ed as mW/MHz. As a comparison, the whole Raspberry Pi A+ uses 1Watt, including a 700 Mhz CPU - a lot more than the meagre 3Mhz suggested \$\endgroup\$ – MSalters Sep 20 '16 at 12:52
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    \$\begingroup\$ It's more useful to refer to "MIPS per watt", as the amount of work done per clock cycle varies wildly. \$\endgroup\$ – pjc50 Sep 20 '16 at 13:12
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    \$\begingroup\$ Well, it depends on what the chip is designed to do. A chip with a TDP of 80W that's designed to run at 3 GHz at 1.2 volts could maybe run on 1V and 1A...but at 1V you're going to have to drop the speed significantly, and to get it to draw 1A you'll have to drop the speed even more. You're not going to get anywhere near 3 GHz in that case. I have no idea what you would actually be able to achieve, though, as I haven't tried it myself. Maybe 3 MHz is a bit pessimistic for an i7 at 1V and 1A. Now, it's certainly possible to design a chip to run at that power level, as you mention. \$\endgroup\$ – alex.forencich Sep 20 '16 at 13:44
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    \$\begingroup\$ They are not simple. In fact they are the one of most complex things we have ever built. \$\endgroup\$ – joojaa Sep 20 '16 at 18:04
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    \$\begingroup\$ Modern Intel/AMD CPUs use at least some dynamic logic that would actually fail to work if clocked too low. Intel Skylake (for example) has a minimum efficient frequency/voltage point. To hit even lower power/throughput levels for SoC, it switches a core in and out of sleep at a variable duty cycle (>=800us at maybe ~1GHz (most efficient f), rest in sleep). See Efraim Rotem's IDF2015 Skylake power-mgmt talk, at about 53 minutes in \$\endgroup\$ – Peter Cordes Sep 20 '16 at 20:01
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According to Wikipedia, top CPUs released in 2011 had some 0.5 to 2.5 billions of transistors. Assuming a CPU with 1 billion of transistors consumes 64A of current, the average current is only 64nA per transistor. Considering operation frequencies of several GHz, it's actually surprisingly little.

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  • \$\begingroup\$ Is for higher operating frequency of CPU required higher current? \$\endgroup\$ – Lu Ka Sep 20 '16 at 19:26
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    \$\begingroup\$ Generally current \$I \approx I_0 + kf_CV^2\$ where fc is the clock frequency and k is a constant and V is the operating voltage, and I0 is the leakage current. k will vary depending on how many transistors are switching at a given time as well as with the chip design. \$\endgroup\$ – Spehro Pefhany Sep 20 '16 at 19:28
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    \$\begingroup\$ At this point, we can put more transistors on a CPU than we can use at the same time without melting it. So at any given time, a large fraction of the chip is Dark Silicon: not powered up, but sitting there waiting to be used while other parts of the chip (with different specialized functions) are powered down. e.g. the vector floating point hardware, the vector integer multipliers, and the vector shuffle units can't all be saturated at once, but they each have high throughput when used alone. Also, large caches don't switch much. \$\endgroup\$ – Peter Cordes Sep 20 '16 at 20:34
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    \$\begingroup\$ This is a big factor in CPUs gaining more and more specialized hardware, like AES and SHA crypto instructions, and Intel's BMI2 (especially PEXT / PDEP bit-extract/deposit). Something to do with the transistor budget that can speed up some workloads but doesn't have to be powered on when not in use. \$\endgroup\$ – Peter Cordes Sep 20 '16 at 20:37

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