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This is my circuit in relevance to my question:

circuit

I apologize for the messy wiring, but I did it that way to make my PCB production substantially easier.

My problem is I only have 10 wires available to write to and read from RAM with. Of those 10, 8 are connected directly to the P1 pins of an AT89C2051 for direct data communication with the micro controller. I have used up all my remaining GPIO pins for other tasks and I only have two remaining. One for clock, and one for data.

I can easily select a ram address with this circuit, but what I want to do is be able to choose whether to read from or write to ram without using any more GPIO lines from the micro controller.

One source online states I can't connect WR and OE with an inverter for bus contention reasons.

I thought to use the 74HC138 decoder chip but then I think there's a more efficient way where the data loaded in serially won't trigger a WR or OE pin unnecessarily, but I'm not sure. Perhaps the 74HC138 is the wrong way to go?

How do I solve this?

P.S. I have quite a few parallel ram chips and I don't want to be suggested to replace my circuit with serial ram because I want to use my RAM I have.

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    \$\begingroup\$ Maybe you can use an I2C I/O expander, but it depends on your speed requirements and how much control you have over those two pins you have. \$\endgroup\$ – pipe Sep 20 '16 at 2:34
  • \$\begingroup\$ Messy drawings don't make PCB productions easier. \$\endgroup\$ – Olin Lathrop Jan 19 '17 at 14:48
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That approach simply won't work. Every time you transmit 2 ones followed by a zero you will get a write to RAM, and this will occur for any number of addresses. Your problem is that your "activation code", 110, is not excluded from your data addresses. Since your addresses can be any combination of 13 bits, your activation code must be 14 bits or greater, which will be cumbersome. For instance, if you pad your address with two leading zeroes, and use a 15 bit code (14 ones and another bit to determine OE or WR, you can do what you want.

And I'll give you a pass on your mapping of QA, QB and QC to A6, A4 and A2. I'll assume that you have some really bizarre and creative reason for doing that, but I shudder to think about trying to keep the coding straight.

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  • \$\begingroup\$ yes the address mapping is like that to make design on a single sided circuit board much easier. \$\endgroup\$ – user116345 Sep 20 '16 at 3:30
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You really need an output latch signal so you can use 74HC595 and not have the outputs change until to output latch signal goes from low to high. Maybe you can up with a clever way to use a shift register, or a pair, that goes low and then high when the 16th shift clock goes high.

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You should read up on the use of ALE (Address Latch Enable) lines in the 8085 architecture and its descendants. It was a cheap way to multiplex bus lines between address and data, reducing the IC pin-count by 7. Your application is similar, even if you have reduced the bus further.

With 2 GPIO lines, a mux and a couple of 8-bit latches you can represent 4 states:

  1. Idle
  2. Load address byte high
  3. Load address byte low (and Read/Write)
  4. Execute Read/Write

Making sure to represent these states in Gray code (to eliminate unwanted transitions) would provide all of the desired functionality much faster and safer than your current implementation.

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