# I need to derive a lower frequency clock from the main clock and sample it in verilog

I have been successful in deriving the clock, but am unable to sample and check the results in the test bench. Attaching the code and the written test bench. Need to find a way to do away with the error->

Line 68: Target of concurrent assignment or output port connection should be a net type.

The program-

module clk_div
#(
parameter WIDTH = 4, // Width of the register required
parameter N = 6
)
(clk,reset, clk_out);

input clk;
input reset;
output clk_out;

reg [WIDTH-1:0] reg1;
wire [WIDTH-1:0] next;
reg clk_tmp;

always @(posedge clk or posedge reset)

begin
if (reset)
begin
reg1 <= 0;
clk_tmp <= 1'b0;
end

else if (next == N)
begin
reg1 <= 0;
clk_tmp <= ~clk_tmp;
end

else
reg1 <= next;
end

assign next = reg1+1;
assign clk_out = clk_tmp;

endmodule

//-----------------------------------------------------------------------------------------------------

module sampling(clk_out, clk, result);
input clk_out;
input clk;
output reg [3:0] result;

clk_div inst (clk_out,rst,result);

reg [3:0] reg2;

always @ (posedge clk_out)
begin
if (clk==1'b1)
reg2[0]<=1;

else
reg2[0]<=0;

reg2<={reg2[2:0], clk_out};
assign result = reg2[0];

end
endmodule


It's test bench-

module tb1;

// Inputs
reg clk_out;
reg clk;

// Outputs
wire [3:0] result;

// Instantiate the Unit Under Test (UUT)
sampling uut (
.clk_out(clk_out),
.clk(clk),
.result(result)
);

initial begin
// Initialize Inputs
clk_out = 0;
clk = 0;

// Wait 100 ns for global reset to finish
#100;

clk=1'b1;
forever #10 clk=~clk;

end

endmodule

• It will be helpful if you add a comment in the code pointing out which line is line 68. – The Photon Sep 20 '16 at 3:14

Your problem is probably this line:

assign result = reg2[0];


Because earlier you declared

output reg [3:0] result;


Nets declared as reg type can only be assigned within procedural blocks (always and initial blocks).

If you want to use continuous assignment, you must declare the variable as a wire type.

In the case of an output, that just means removing the reg keyword from the declaration:

output [3:0] result;

• Thanks The Photon! I did as you said.. now it gives me the following error-> Line 81: Procedural assignment to a non-register result is not permitted, left-hand side should be reg/integer/time/genvar Line 81 here is-> assign result = reg2[0]; – Ameya Sep 21 '16 at 15:48
• @Ameya, your assign statement should not be inside any always block. – The Photon Sep 21 '16 at 15:55