This question is specifically about the Spartan 6-75LXT (FG676) but can be applied to any Spartan 6 (and possibly other Xilinx parts as well).

When using the GTP wizard by itself, there are 2 pairs per tile. In this specific case, they are MGTTXx0_101/MGTRXx0_101 and MGTTXx1_101/MGTRXx1_101. This is on tile GTPA1_DUAL_X0Y1. When using the PCIe integrated endpoint, MGTTXx0_101/MGTRXx0_101 is the hard-coded transceiver.

I made a mistake in my board design, and assigned a transceiver pair (with a different purpose than PCIe) to MGTTXx1_101/MGTRXx1_101. I am wondering, does anyone know if there is a way to still use this channel AND the integrated endpoint. The only other 2 options I can see are both unattractive. Re-design the board or design my own soft-core PCIe interface using the GTP wizard.

I am hoping for an easier option.

Thanks in advance.

  • \$\begingroup\$ For a prototype, I'd re-wire the board you have. Assuming you brought out the relevant pins to accessible vias... \$\endgroup\$
    – user16324
    Commented Sep 20, 2016 at 18:41
  • \$\begingroup\$ Yes. But I hadn't. The balls are safely hidden behind 12 layers of FR-4. And even if I found someone to do some precision drilling, there are traces in the layers between the balls. I had already checked that. \$\endgroup\$ Commented Sep 20, 2016 at 18:47

1 Answer 1


Looks like there is an option for doing that on the last page of the wizard, according to the manual. Is there some reason you can't reconfigure the endpoint IP core to use the correct transceiver channel?

Edit: Just used coregen to generate a PCIe core for xc6slx75t-fgg676 and I had no issues selecting that specific transceiver. The example design lists the PCIe transceiver pins as B8, A8, D9, and C9. So just reconfigure your core with coregen and you should be good to go.

Edit 2: NVM, just realized that you want to use one channel of the GTP transceiver for PCIe and the other channel for something else. It looks like you may need to go tinkering in the bowels of the coregen generated code, but it seems like it should be doable. The generated code seems to use transceiver wizard generated code for the GTP portion, so it very well could be possible to either connect the hard core to a properly reconfigured transceiver wizard core OR to bring out the required interfaces of the transceiver in the coregen generated files for the PCIe core. The PCIe hard core is just an instantiation of the PCIE_A1 primitive, so I don't think there will be any issues with reworking the coregen output to do what you need.

  • \$\begingroup\$ I think I see what you mean. Right now, I just use the NGC file produced by CoreGen. But if I instead used the wrapper files and INST in my UCF, then I may be able to edit those files to use my second channel. I had previously thought that those files were just simulation files for the NGC. Are they interchangeable for implementation? For example, if I delete the NGC file and then place the wrapper file in my project; my connections look good. But if I place the NGC file BACK in, it kicks my wrapper file out. Does this match your understanding? \$\endgroup\$ Commented Sep 21, 2016 at 1:50
  • \$\begingroup\$ When I ran coregen just now, didn't even generate an ngc file. So I think it will work just dandy. \$\endgroup\$ Commented Sep 21, 2016 at 1:57
  • \$\begingroup\$ Aha, it looks like it's set up to generate the ngc file from the HDL files when you synthesize the whole project in ISE. But it seems like there's no reason you HAVE to generate that - i.e. it should be possible to ignore the xco file from coregen and just pull in the sources directly. Yes, the synthesis could take a bit longer, but I don't see any reasons why it wouldn't work. \$\endgroup\$ Commented Sep 21, 2016 at 2:01
  • \$\begingroup\$ Interesting... We must be on different versions. I will get to trying it first thing tomorrow. But it does lead me to a different question. If it is just this easy to modify, can you speculate why Xilinx wouldn't claim that Spartan 6 can do 2 lane PCIe? I would think that would be a big selling point? \$\endgroup\$ Commented Sep 21, 2016 at 2:02
  • \$\begingroup\$ Well, the hard core only supports 1 lane, and there's only 1 hard core. I think you could do 2, 4, or maybe even 8 lanes if you implement the PCIe core in soft logic. Or you can switch to the Artix-7 and get 8 lanes of PCIe gen 2 with an integrated hard PCIe IP core. \$\endgroup\$ Commented Sep 21, 2016 at 2:07

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