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I have 3 paralleled MOSFETs which will be attached to a single heatsink.

I am trying to calculate maximum possible power dissipation and required heatsink thermal resistance Rsa(sink-ambient).

I start from the general equation:

  • Rja(junction-ambient) = Rjc(junction-case) + Rcs(case-sink) + Rsa(sink-ambient).
  • Rsa = Rja - Rjc - Rcs
  • Rsa = (Tj-Ta)/Pd - Rjc - Rcs

Ta is ambient temperature and is choosen to be 45 °C due to forced air cooling and enclosed device.

Tj is arbitrarily choosen to be 150 °C with 25 °C headroom (Tjmax = 175 °C) which should be enough? Or should I go for more headroom?

Rcs includes resistance of thermal compound and insulating pad.

And here is where I have some doubts. Since all MOSFETs will be attached to the same heatsink how do I calculate Rsa?

Lets say that power dissipation of each MOSFET will be 20W thus 60W in total. Do I plug 60W into the above equation and multiply Rjc and Rcs by 3 (as their values are for single MOSFET)?

Or do I plug in 20W, calculate Rsa for single MOSFET but divide final result by 3 (due to 3 MOSFETs)?

The latter method seems more "right" to me, dont know why tho...

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  • \$\begingroup\$ Each power source adds to total power dissipated in sink but the resistance that results in temp drop from heatsource does not change so if you have 100x 1W devices sharing 1 sink or 1W with 100W the heatsink will be the temperature but the junction temp rise will be 100x bigger if only using 1 device. ( not because Rjc has changed, but because Pd source is bigger.)! The Rjc, Rcs & Rsa does not change . Sharing loads with multiple FETs does not cool the sink with more power, it cools the junctions. and now more heat has to be removed from sink \$\endgroup\$ – Tony Stewart Sunnyskyguy EE75 Sep 20 '16 at 23:02
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Assuming that each mosfet dissipates the same power, you can model them as a signle mosfet (that dissipates then total power), with Rjs (junction-sink) = 1/3 *( Rjs-of-a-single-moseft). The explanation is that the three Rjs'es are in parallel.

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  • \$\begingroup\$ I would think the Rjs stays the same and Pd is x3 for 1 device as all the Pd accumulates on same sink. \$\endgroup\$ – Tony Stewart Sunnyskyguy EE75 Sep 20 '16 at 21:42
  • \$\begingroup\$ I don't understand what you mean. I added (that dissipates the total power). Does that clarify it for you? \$\endgroup\$ – Wouter van Ooijen Sep 20 '16 at 22:09
  • \$\begingroup\$ Pd(tot) = 3Pd but Rjs(tot) = Rjs (one) not 1/3 Rjs(oneFET) . The thermal resistance is not reduced. \$\endgroup\$ – Tony Stewart Sunnyskyguy EE75 Sep 20 '16 at 22:32
  • \$\begingroup\$ Yes, the total power is 3 times the individual power, but that total power flows to the heatsink via three parallel paths: the Rjs'es of the three separate transistors. So the one virtual 'supertransistor' that dissipates all the power has an Rjs that is 1/3 of the Rjs of each physical transistor. \$\endgroup\$ – Wouter van Ooijen Sep 20 '16 at 22:38
  • \$\begingroup\$ Ok I understand you but disagree. There is no reduction in thermal resistance since power is x3 but Rcs is the same.. Repeat logic for 1000 FETs on same heatsink... YOur assumption results in 3PD/*1/3Rcs = Pd*Rcs ( same as one device. Which we know is not logical sharing same heatsink.) Temp. rise on sink is sum of all or 3Pd *(Rjc+Rcs+Rsa) with no change in any resistance \$\endgroup\$ – Tony Stewart Sunnyskyguy EE75 Sep 20 '16 at 22:51
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I would neglect number of parallel devices and lump all the Power in the model of 1 part with same Rjc as 1 device.

The logic uses Norton Current equivalent power source so the currents add into load heatsink to 3A with very little going to the other sources due to the R value of sink being small compared to junction to case, if not then a more complex result degrades the heat rise result in the junctions.

If you understand the total power into the sink does not change ( assuming there is a heatsink. You can simulate with/without a heatsink here.

Simulation and proof.

Then press reset for dynamic temp rise enter image description here

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  • \$\begingroup\$ Your step from the first circuit to the second is wrong. In the first circuit you can prove that the voltage at the top of your three current sources/sinks is the same, so you can short those three nodes. Now you can clearly see that the R1+R4 is in parallel with R2+R5 and R3+R6. \$\endgroup\$ – Wouter van Ooijen Sep 20 '16 at 23:08
  • \$\begingroup\$ I suggest you estimate the heatsink temp in both models and ask yourself if you put in 60W into 3 FETs or 60W into 1 FET should the heatsink be the same temp? or 1/3 the rise? at the sink I think it should be the same Temp at heatsink above ambient. in both cases. Thus Rth does not change.. My attempt to use current source model isolates each source and load R is smaller than junction. \$\endgroup\$ – Tony Stewart Sunnyskyguy EE75 Sep 20 '16 at 23:13
  • \$\begingroup\$ The heatsink temperature will be the same, but the junction teperature will be lower for the 3 transistor case. \$\endgroup\$ – Wouter van Ooijen Sep 20 '16 at 23:21
  • \$\begingroup\$ That is due to 1/3 Ptot (not 1/3Rjc) \$\endgroup\$ – Tony Stewart Sunnyskyguy EE75 Sep 21 '16 at 0:03
  • \$\begingroup\$ I don't agree, and I don't think our disussion will lead to an agreement. PS your 1 Ohm resistors should be named Rsa (sink-abient). \$\endgroup\$ – Wouter van Ooijen Sep 21 '16 at 0:06

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