# Dynamic and Active Leakage in CMOS

I studied various techniques to reduce the leakage power consumption in CMOS design. Leakage currents can be static and active. I understand the meaning of static (standby) leakage, but I am confused about the active leakage. Does this occur during transition phase (like that of dynamic power)? How to calculate this particular (active) leakage?

Active leakage refers to the leakage when both FET's are slightly on. This occurs during the transition of the gate from one logic level to another, due to non-infinite slope at the transistor gates.

In the image below, active leakage is labelled with short circuit current. The amount of active leakage depends on the input slope to the gate. If the slope is very fast, both transistors will be on for less time than if the transition is very slow.

Another effect which is more hidden is that there is a finite delay between transitions at adjacent transistors. This is caused by wire resistance and parasitic capacitance. So even with an infinite slope (impossible, but just for this thought experiment), there will be some finite delay between transitions at each transistor's gate in the CMOS logic gate. This is a short crowbar current.

Passive leakage refers to leakage not caused by switching, but just standby through the maximum resistance FET (completely turned off).

If you want to measure active leakage, simulate the gate switching at a reasonable input slope with a reasonable output load (the input slope will be strongly proportional to the active leakage power). Now measure the current in the non-active FET. For example if the output is rising, measure the current in the NMOS. If the output is falling, measure the current in the PMOS. This current is not being used to charge or discharge the output capacitance, but rather is crowbarring through both FET's during the time when both are slightly turned on.

Multiply this by your supply voltage and you have instantaneous power. Or you could integrate the current during the transition window to calculate the energy per cycle, and from here find the power as a function of frequency.

To turn a MOSFET on you have to raise the gate voltage to (say) 5V. In doing so you charge the gate-source capacitance to 5V. If the capacitance is 5 pF then the energy put into the gate-source junction is $CV^2$/2 or 62.5 pJ.

When you turn that MOSFET off, that energy is lost as heat and gone.

If this happens ten million times per second then the total lost power = energy x 10^6 = 626 uW. If you have 1000 MOSFETs doing this you have a power dissipation of 625 mW.

There is also the output capacitance of the MOSFET to add to this but is probably less than gate dynamic power loss.

• This refers to active switching power due to capacitance charging/discharging at each transition (provided by driver). I think the OP is asking about active leakage power which is due to a short crowbar between NMOS and PMOS during input transitions (through s/d terminals of both complexes). – jbord39 Oct 21 '16 at 16:03