# Why does Modelsim say that VHDL shared variables must be protected?

So I created a shared variable in a purely non-synthesizeable code.

When compiling ModelSim generates a warning:

(vcom-1236) Shared variables must be of a protected type.

Why is it a warning and not an error if the shared variable must be "protected"?
What does protected even mean in this case i.e protected from what?

The shared variable is just a std_logic.

• Starting in IEEE Std 1076-2002 shared variables are of protected types (accessed by methods instead of assigned or evaluated directly). The default standard revision used by recent Modelsim versions is -2002. – user8352 Sep 22 '16 at 2:16
• What is the northern behind this change for shared variables? Certainly it overcomes some drawbacks that they have right? – quantum231 Sep 22 '16 at 7:36
• Protected Shared Variables in VHDL: IEEE Std 1076a (The first thing that comes up googling using VHDL mutual exclusion protected type). – user8352 Sep 22 '16 at 7:49
• There were issues with vendor implementations of shared variables before 2002. The the newer standard revisions enforce protected types, so shared variables have a well defined behavior: in your designs and in different simulators. That does not mean that all vendors, who claim to support VHDL-2008, have a correct protected type implementation ... !! I have a testcase which shows, that their simulator has the same faulty shared variable implementation like the predecessor product (which supported only VHDL-93) developed by the same company :). – Paebbels Sep 22 '16 at 23:57
• If you use GHDL use -frelaxed-rules switch to relax this issue to warning. – betontalpfa Jun 5 '19 at 16:17

In your case you could replace your shared std_logic variable with a small protected type with an internal variable and set and get procedures. This would get rid of the warning, but provide zero extra protection.