I'm designing a pretty complex two layer board - I should really go for a 4 layer one, but that's not the point here. I'm done with component placing and routing and I'm doing the finishing touches such as making sure the ground planes cover most of the board and are well stitched together (a.k.a ground gridding).

In certain areas, I have signal traces (e.g. SPI) layed out over a ground plane, then a power trace (14V), then another ground plane. There is no way I can move this power trace out of the way, so I thought I could let the signal return currents go through it by having some decoupling capacitors (100nF) between the power trace and ground planes, right under my signal traces.

Here's an image of what I'm thinking:

Signal over decoupling capacitors

Is this a good idea to reduce the signal loop area and control EMI?

  • \$\begingroup\$ I don't see the point for all this complexity and I am sure that adding capacitors increases the noise of the circuit. Digital signals going through a power trace isn't critical as long as you place decoupling capacitors next to the powered devices. The digital signals are relatively fast edges and shouldn't affect much the power trace. Most ICs also have a common noise rejection on its power supply pins, so it really isn't a big deal. Also, your SPI trace is perpendicular to the power trace, which means the crosstalk will be minimal. \$\endgroup\$
    – lucas92
    Sep 22, 2016 at 14:14
  • \$\begingroup\$ I'm not as worried about signal integrity or coupling between traces, this is not the point of my question. The signal return path is pretty long and not right under the signal traces, which is what is recommended usually. I remember reading about the technique I'm trying to apply in the case of USB signals and some application note recommended using capacitors to let the return current flow as close as possible to the signal traces on the other layer. \$\endgroup\$
    – user122244
    Sep 22, 2016 at 14:20
  • \$\begingroup\$ Oh, you are worried about the ground return path. I misunderstood the question. I'm not sure about that one, you will probably end up adding noise to the power trace right? \$\endgroup\$
    – lucas92
    Sep 22, 2016 at 14:31
  • \$\begingroup\$ That's what I'm wondering too. The currents involved are really small and the power trace is filtered near every IC connected to it (bypass caps) so I'm not sure if it will be an issue. \$\endgroup\$
    – user122244
    Sep 22, 2016 at 14:38
  • \$\begingroup\$ But if you do it this way, what will set the DC reference to the local GND ground? You need an another trace for the DC reference? \$\endgroup\$
    – lucas92
    Sep 22, 2016 at 14:46

1 Answer 1


You are correct in your understanding. The return current from any signal will want to follow the same path as the signal itself using an adjacent ground or power plane. If the ground plane is broken it will still find a path back to the source of the signal, but by a longer less optimal path which can result in higher emissions and worse immunity. Whether this is a problem in your design depends on many factors such as the clock speed of the signals, and more importantly the speed of their edges.

If you think it may be a problem (and presumably you do) then the best solution is to use a 4 or more layer board so you have an unbroken ground plane. Using a 2 layer board you could add a 0805 or 1206 zero-Ohm link to stitch the two ground planes together at the point where they are broken to provide the current return path.

  • 1
    \$\begingroup\$ I thought so. I might go for a 4 layer board in the next iteration of my prototype, but as of now it is not really an option (and EMI compliance not an issue yet). The slot created by the power trace is too wide to bridge it with a zero ohm, hence my capacitor solution. I also found this paper that suggests that capacitor stitching is suboptimal but viable for frequencies (or edge speed) less than 100MHz. \$\endgroup\$
    – user122244
    Sep 22, 2016 at 15:12
  • \$\begingroup\$ I forgot to mention that the above linked paper directly connects two reference planes whereas I would have to "route" the signal return current through an intermediate trace. \$\endgroup\$
    – user122244
    Sep 22, 2016 at 15:20
  • 2
    \$\begingroup\$ I don't think that your capacitor solution will cause problems, I just don't think it is quite as good as directly stitching the planes with 0R. \$\endgroup\$
    – Steve G
    Sep 22, 2016 at 15:29

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