Never worked with PowerPC, but from e200z3 Power Architecture™
Core Reference Manual, you should be able to get a better understanding.
Capter 10 in the MPC5534 Microcontroller Reference Manual mentions this manual: Interrupts implemented by the MCU are defined in the e200z3 PowerPC tm Core Reference Manual.
The Core Reference Manual section 22.214.171.124 has this to say about the IVPR:
The IVPR, shown in Figure 2-16, is used during interrupt processing to determine the starting address for the software interrupt handler. The value contained in the vector offset field of the IVOR selected for a particular interrupt type is concatenated with the value in the IVPR to form an instruction address from which execution is to begin.
It the lists the bit fields of that register, of which there is only one: The Vector Base:
Defines the base location of the vector table, aligned to a 64-Kbyte boundary. Provides the high-order 16 bits of the location of all interrupt handlers. IVPR || IVORn values are concatenated to form the address of the handler in memory.
IVORs, shown in Figure 2-17, hold the quad-word index from the base address provided by the IVPR for each interrupt type.
Additionally, section 4.5 says:
The value in the vector offset field of the IVOR assigned to the interrupt type is concatenated with the value in IVPR to form an instruction address at which execution is to begin.
After the interrupt priority logic has decided on which interrupt vector to activate, the program counter will jump to the address
IVPR || IVORn.
Note that each interrupt only has space for four instructions, so if you want to do some heavy lifting you have to branch. Setting a quick flag or toggling an I/O pin should be possible without any branches.