I am working with Freescale MPC5534 based on PowerPC arch. I am not able to understand how the address of a particular ISR is calculated during runtime. There are three registers involved, INTC_IACKR, INTC_IVPR, INTC_IVOR, and the final value of the interrupt vector corresponding to a particular ISR is based on the values loaded to these registers at runtime i.e, some base_address + prefix + offset from the three registers, respectively.

I am just not able to understand the connection these three values and how the vector is calculated from collective value of all these registers.

People who have worked on any PowerPC based controllers might be able to help.


2 Answers 2


Never worked with PowerPC, but from MPC5534 Microcontroller Reference Manual, INTC_IACKR contains the vector table base address and the vector that caused the interrupt request to the processor. I did not find any info regarding INTC_IVPR or INTC_IVOR.

The interrupt request to be sent to processor is determined by a "Priority Arbitrator" using the INTC_PSR (priority select) and INTC_CPR (current priority) registers. You'd want to refer to Chapter 10 for more info on it.

  • \$\begingroup\$ You'll find references to IVPR and IVOR, and interrupt vector calculation in pages 3-16, 10-2 of the same manual. I'm just not able to comprehend it. If you could give any leads..? \$\endgroup\$
    – stenvar
    Commented Sep 24, 2016 at 9:56

Never worked with PowerPC, but from e200z3 Power Architecture™ Core Reference Manual, you should be able to get a better understanding.

Capter 10 in the MPC5534 Microcontroller Reference Manual mentions this manual: Interrupts implemented by the MCU are defined in the e200z3 PowerPC tm Core Reference Manual.


The Core Reference Manual section has this to say about the IVPR:

The IVPR, shown in Figure 2-16, is used during interrupt processing to determine the starting address for the software interrupt handler. The value contained in the vector offset field of the IVOR selected for a particular interrupt type is concatenated with the value in the IVPR to form an instruction address from which execution is to begin.

It the lists the bit fields of that register, of which there is only one: The Vector Base:

Defines the base location of the vector table, aligned to a 64-Kbyte boundary. Provides the high-order 16 bits of the location of all interrupt handlers. IVPR || IVORn values are concatenated to form the address of the handler in memory.


IVORs, shown in Figure 2-17, hold the quad-word index from the base address provided by the IVPR for each interrupt type.

Additionally, section 4.5 says:

The value in the vector offset field of the IVOR assigned to the interrupt type is concatenated with the value in IVPR to form an instruction address at which execution is to begin.


After the interrupt priority logic has decided on which interrupt vector to activate, the program counter will jump to the address IVPR || IVORn.

Note that each interrupt only has space for four instructions, so if you want to do some heavy lifting you have to branch. Setting a quick flag or toggling an I/O pin should be possible without any branches.


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