ModelSim is unable to compile this in VHDL:

constant mem_size_bytes: integer := x"FFFFFFFF";

It says:

Bit string literal found where non-array type std.STANDARD.INTEGER was expected.

Similarly for;

if address< x"3FFFFF" then

it says

Operator "<" is ambiguous

I keep running into this problem. How in the world am I supposed to use hexadecimal numbers in VHDL with integer types like integer, natural and positive? Its just that specifying something hexadecimal is more convinient at times than having to use the calculator to determine what something is in radix-10. I had hoped that the tool will automatically know what the literal means since it is preceded by x which marks it as hexadecimal numeric quantity!!!

So, when assigning literals to constants or when using literals in comparison operator how does one qualify the literal? In other word for a literal constant value like "1010", how do explicitly tell the compiler if this is a string or std_logic_vector or unsigned or signed?

  • 1
    \$\begingroup\$ See based_literal, where the the negative one expression (for the minimum supported integer size) would be 16#FFFFFFFF#. Integers are scalar while bit strings and string literals are associated with arrays of character types (and std_ulogic is a character enumerated type). Simply put, integers don't got bits. \$\endgroup\$ – user8352 Sep 23 '16 at 5:26

VHDL supports arithmetic values but it has to know if they are signed or unsigned. I recommend using the numeric_std library to support these types.

VHDL is strongly typed. For your first question, I would use:

EDIT: I have erased a prior more complex form and used this simpler one after Brian Dummond's comment

constant mem_size   : integer := x"FFFF_FFFF";

The second, supposing address is an std_logic_vector, has to be written:

if unsigned(address) < x"3FFFFF" then
  • 2
    \$\begingroup\$ Downvoted for recommending unnecessary type conversions. Prefer the simpler solution of using the right syntax 16#3fffff# for based integer literals. \$\endgroup\$ – Brian Drummond Sep 23 '16 at 10:29
  • \$\begingroup\$ I did not know about this # format. None of the resources I have show these. I will try it out. \$\endgroup\$ – quantum231 Sep 23 '16 at 13:51
  • \$\begingroup\$ Ok, how does one qualify the literals that are string of bits like "1010" as std logic vector, unsigned, signed or something else? \$\endgroup\$ – quantum231 Sep 23 '16 at 13:54
  • 1
    \$\begingroup\$ For vectors of bits or of std_logic, either "1010" or x"A" work. For base 2 integer literals, 2#1010#. And of course, 6 * 9 = 13#42#. \$\endgroup\$ – Brian Drummond Sep 25 '16 at 10:28
  • 1
    \$\begingroup\$ @quantum231 then none of your resources are a decent textbook. I still turn to Ashenden "Designer's Guide to VHDL" most often. \$\endgroup\$ – Brian Drummond Sep 25 '16 at 10:32

Your Answer

By clicking “Post Your Answer”, you agree to our terms of service, privacy policy and cookie policy

Not the answer you're looking for? Browse other questions tagged or ask your own question.