They all got to Vbat- but path is explicitly used only by Analog loads or digital loads by layout and not shared.
Layout is your choice, research how ADC boards do this.
Since Inductive current noise must be minimized, and Inductance is determined by length/width ratio of tracks, and V=L di/dt, you want wide tracks or copper pour to high switched currents. Also consider stray coupling capacitance in layouts.
For high current switched loads, consider ESR of output caps and min/max range if specified in datasheet. Usually one or two caps ensures good switched load regulated noise, if there is any on these 200mA devices.
Having two separate regulators gives low Zout and excellent isolation on Vout and these parts have excellent common mode Vin noise noise rejection, but two IC'/ may not be necessary in some cases.... unless one becomes the Analog Vref for say an ADC.
Since n* CMOS gates switching at once is n* C load with low ESR/n it's Voltage Source and ground return must be as ideal as possible.
Namely, for 5% ripple, 1/20th of the load ESR using a small C >yet 20x. Bulk E-Caps and batteries do not have this low ESR in the 0.35/risetime equivalent frequency range. Often high SRF high Q 100pF to 1nF caps are necessary close to the point of distribution. THis translates into 50MHz ~1GHz and depends on Cap SMD size.
The reason the above is critical is that a small T= RC load , with a transient response is effectively the ratio of Z(f) for source/load up to the frequency of 0.35/Tr.