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Summary
For a mosfet, transition from saturation to triode region happens much quicker than from triode to saturation. Why?

Details
UPDATE: the load resistor was removed. enter image description here Fig.1: Schematic

enter image description here Fig.2 Transient analysis

Notes:
1) BSIM4 SPICE model of MOSFET is used. Model parameters used (file cmosedu_models.txt) can be downloaded here.

  • Initially, the transistor is in saturation region (Vgs=350mV > Vth=280mV, Vds=V(out)=400mV > Vdssat=50 mV). Idssat=10uA.
  • After Vgs has increased, the transistor moves into triode region and its Vds goes down from 400 mV to 8 mV (below Vdssat).
  • Then, the opposite transition happens.
  • Transistion from triode to saturation takes around 6 ns, while transition from saturation to triode happens almost instantaneously.Why such a difference?

Appendix
enter image description here
Fig.3: Transistor parameters (for the operating point corresponding to Vgs=350mV). Source: CMOS Circuit Design, Layout, and Simulation, Third Edition. R.J. Baker. Page 300.

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  • \$\begingroup\$ Tried with Level 3 MOSFET model. The same effect. \$\endgroup\$ – Sergei Gorbikov Sep 24 '16 at 16:14
  • \$\begingroup\$ LTSpice mode download URL. \$\endgroup\$ – Sergei Gorbikov Sep 24 '16 at 16:58
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I'm going to post an answer but it's really adding more details to Mario's correct answer and, if he wants to strip my answer of anything I'll just delete this.

A randomly googled MOSFET output (DS) capacitance versus drain voltage: -

enter image description here

It doesn't matter what MOSFET you use, the drain capacitance (\$C_{OSS}\$) at 1V (as per Sergei's table in his question) will increase to something like 4 times that value when the MOSFET is fully on in the triode region. The drain voltage is 8 mV and, as you can see \$C_{OSS}\$ rises to about 20,000 compared to about 5000 at 1V.

It's all relative and these could be farads, pico farads or fractions of femto farads.

So if the drain capacitance is 6 fF at 1V then it is likely to be in the realm of 24 fF at about 8 mV drain voltage. At 450 mV (as per the waveform in the question), the capacitance could be about 12 fF.

If 24 fF is charged with 10 uA the dV/dt will be 10 uA / 24 fF which is 417 volts per us OR 417 mV per nano second. Here's what it will look like against Sergei's picture (orange is the line I've added spanning between 6 ns and 7 ns and rising from 0 mV to ~417 mV): -

enter image description here

Clearly it's about the same sort of rate as he is seeing and the exponential asymtotic shape is going to be due to non-infinite drain resistance.

It's going to be more complex than this because the \$C_{OSS}\$ falls rapidly as drain voltage rises and, if the equivalent drain saturation resistance were infinite (i.e. a tending towards a true flat line), I would expect more like an exponential rise rather than a linear or asymtotic rise.

Anyway, @Mario, strip out anything you want and let me know to delete my answer.

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  • \$\begingroup\$ I think your answer really hits the nail and is much more elaborate than mine! I'll upvote instead. \$\endgroup\$ – Mario Sep 24 '16 at 18:04
  • \$\begingroup\$ @Mario you are such a gentleman. \$\endgroup\$ – Andy aka Sep 24 '16 at 18:05
  • \$\begingroup\$ Different transistor capacitance is a second-order effect. The primary effect is so obvious that it should not be asked in first place. Initially, the transistor parasitic capacitance is charged up to Vdd. On Vin up, the switch opens with low impedance Rds_on, so the discharge goes at fast rate. Upon Vin down, the switch opens up, having a very high impedance Roff. So the same (or about the same) parasitic capacitance gets charged up at much slower rate. As Mario said. \$\endgroup\$ – Ale..chenski Sep 24 '16 at 18:06
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The different transition times are a result of your particular test setup.

The transition time depends on the parasitic capacitance at the output and the current to charge or discharge it. In your case, for a falling edge discharging is done by the transistor itself and a large current is possible.

In case of rising edge the transistor turns off and the current has to be supplied by the 10uA current source. Because of the resistor at the output this results in an exponential characteristic.

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  • \$\begingroup\$ 1. It has nothing to do with Rload. You may change it to any value. The delay is still there. Take 1G Ohm load. MOSFET capacitance on the order of 6fF which would provide a delay on the order of 6fF*1G Ohm=6 us vs 6 ns seen in the simulation. 2. The transistor does not turn off. Vgs>>Vthn. The transistor is deeply open. It triodes. It is not the same. The current going through in nearly the same. But still 10x for the attempt. \$\endgroup\$ – Sergei Gorbikov Sep 24 '16 at 16:26
  • \$\begingroup\$ I don't get why you're using a 10uA current source. Try it with a voltage and series load or something. \$\endgroup\$ – Ian Bland Sep 24 '16 at 16:39
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    \$\begingroup\$ @Sergei Gorbikov - Maybe I was not clear enough. The delay is due to the fact that you are using a current source which has to provide the current for the rising edge. Replace the current source with a resistive load or a PMOS and you will get a much better result. The resistor only sets the limit for the exponential response. It is not the reason for this behavior. \$\endgroup\$ – Mario Sep 24 '16 at 16:51
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    \$\begingroup\$ @SergeiGorbikov you are not listening to what Mario says - when the FET turns on into the triode region it becomes a low value resistor and removes charge from the parasitic capacitance very quickly. When you go to the saturation region the effective resistance looking into the drain is substantially higher and the parasitic capacitance charges much more slowly. \$\endgroup\$ – Andy aka Sep 24 '16 at 17:04
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    \$\begingroup\$ @Sergei Gorbikov - Usually it is a good approximation to assume that a transistor is completely if Vgs=0. Since the transistor is quite wide and the threshold rather low, it could indeed be necessary to consider the leakage current in this case. \$\endgroup\$ – Mario Sep 25 '16 at 5:27
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note that the effective rise time constant { dt=Coss/(Ic) * dV} is large with 10uA current source and fast with ( RdsOn*Coss )= tF, fall time

Since turn off slew rate is non-linear function of this circuit, an approximation of Coss is Coss= 1ns * 10uA/300mV= 33x10e-12 or 33 pF

When low 8mV/10uA implies an RdsOn (rON?) of 800 Ohms for the switch.

400mV from 600mV Vdd with 1M load implies a leakage of 0.5 MOhm in the current source ??

Coss is a common parameter in MOSFET output capacitance specs.

Some parameters must be different in your model!

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  • \$\begingroup\$ Tony, apologies for my poor education :) But i understood nearly nothing in your answer. What are Coss, RdsOnCoss, etc? Could you please clarify for a barbarian like me? \$\endgroup\$ – Sergei Gorbikov Sep 24 '16 at 16:33
  • \$\begingroup\$ +1. I didn't get the answer completely but you were the first to raise the issue with output capacitance Coss (as used in Andy Aka's answer). \$\endgroup\$ – Sergei Gorbikov Sep 24 '16 at 18:17
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Stealing ideas from Ali Chen, Andy Aka and Tony Stewart and possibly Mario. If you like this answer, pls upvote their posts.

Summary
After the large increase of the overdrive voltage, the channel resistance drops substantially providing a fast route for discharge current. After the overdrive voltage goes down again, the mosfet can only be charged with the current source what determines the MOSFET rise time.

Second order effects are:
1) During the charge phase there is a leakage through the MOSFET, thus estimating the rise time simply as \${{C\Delta U} \over I}\$ is not entirely correct. Instead, the rise time should be longer because some portion of the current from the current source bypasses the capacitor (transistor).
2) The transistor output capacitance increases several times when moving from saturation to triode.

The both second-order effects explain an exponential growth of Vds instead of a linear one as predicted by the formula.

Details
enter image description here
Fig.1 Transition from saturation to triode.

![enter image description here Fig.2 Transition from triode to saturation.
Note a different scale.

1) The assumption is that channel resistance adjusts very rapidly to Vgs, which makes sense, I think.
2) Since capacitance changes with Vds (V(out)), it was assumed the capacitance changes relatively "slowly", so in the simulation it was assumed to be constant and as at the beginning of the transition. A more precise simulation would be with capacitance value linked to the value of Vds.

Numerical delays (tens of picoseconds for discharge and several nanoseconds for charge) in this simplified model are close to the ones presented in the question, what should validate this answer.

Appendix enter image description here
Fig.3 IV curves used for calculating channel resistances.

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