I have question about the AXI stream transfer. In the AXI stream slave, I want to capture the data coming through the AXI_Slave_TDATA and then process them (for example multiply each byte of data by 2) and then further transfer it as stream to another IP. What is the VHDL code which processes the stream of data entering the AXI_Slave Stream and then transfer them as stream to another IP? Any example would be helpful
You have posted several FPGA and PL implementation questions. The problem is that these questions are complex and are not easy to answer. I would suggest you to watch several dozens of Xilinx video tutorials just to have a general idea of how things work and what should be expected. Then, there are hundreds of datasheets like UG761 that you can read and get your answers from. Use Xilinx DOC Navigator. Dive into it.
You are asking for an example - I bet there is one somewhere in the documentation - and it is not as simple as two lines of code. Follow these series of videos - the guy focuses on PS-DDR-DMA transfers and gives an introduction to AXI4 interface.
You can take a look at the Xilinx AXI-stream IP example design.
In Vivado, open a new empty project. Tools -> Create and package a new AXI ip. And go through the wizard.
When asked, choose "Create a new AXI peripheral". This will generate example code for you for what an AXI peripheral looks like and create a barebones project to start from.
Until you provide more details, the only answers that can be provided are about AXI stream in general.
Transfers in AXI stream take place when tvalid and tready are both high, with tvalid being driven from the source and tready being driven from the sink. When your core is ready to receive data, set tready high and read in fresh data when tvalid and tready are high. To send data, drive tvalid high along with the new data. Hold the data constant and tvalid high until you get a high level on tready. Then either drop tvalid or place new data on tdata. If you want to use a framed protocol, mark the last transfer of the frame with high tlast. Make sure to only transfer tlast when you transfer tdata (only accept or update when both tvalid and tready are high).