In Verilog I can use the $finish function to halt the simulation, but my search for the similar option in VHDL has failed so far.
The closest solution that I found online is to use this code in my VHDL testbench:
stop_simulation :process begin wait for 1000 ns; --run the simulation for this duration assert false report "simulation ended" severity failure; end process ;
How do you set the time for your simulation in VHDL? For example if I want my clock to run for 10 us, then what is the STANDARD option to achieve this?