In Verilog I can use the $finish function to halt the simulation, but my search for the similar option in VHDL has failed so far.

The closest solution that I found online is to use this code in my VHDL testbench:

stop_simulation :process
   wait for 1000 ns; --run the simulation for this duration
   assert false
       report "simulation ended"
       severity failure;
end process ;

How do you set the time for your simulation in VHDL? For example if I want my clock to run for 10 us, then what is the STANDARD option to achieve this?

  • \$\begingroup\$ hi ehsan . if u wanna make halt in simulation you should use wait for 1000 ns; it's work fine.and if you're persian i can help you easily. \$\endgroup\$ Commented Sep 24, 2016 at 17:53
  • \$\begingroup\$ Yes I am Iranian. So that code is the STANDARD way to halt the simulation in VHDL? \$\endgroup\$ Commented Sep 24, 2016 at 17:59
  • 7
    \$\begingroup\$ That's not the STANDARD way but it works and it's the recommended way in at least one textbook (Janick Bergeron, "Writing Testbenches"). Nowadays you'd just call std.env.stop; instead (and set the compiler options to VHDL-2008). \$\endgroup\$
    – user16324
    Commented Sep 24, 2016 at 20:31
  • \$\begingroup\$ Just put a wait; statement after a wait for ... s; statement. \$\endgroup\$
    – lucas92
    Commented Sep 26, 2016 at 17:47

1 Answer 1


Two ways are commonly used:

Stop the clock (or clocks). That way there are no more events, and the simulation stops. Sometimes, there is a signal (for instance called done) that turns of the clock generator. The testbench asserts the done signal when all tests are completed.

Report a failure. This is not so elegant, but many people use it. A severity of failure will cause the simulator to stop. report "simulation finished successfully" severity FAILURE;

Stop procedure A third way, only available since VHDL 2008 is to call the procedure stop, in the env package of the std library. For instance, like this: std.env.stop;

  • \$\begingroup\$ How does the simulator observe the done signal? You've missed the point of the question, I think. \$\endgroup\$ Commented Sep 26, 2016 at 16:20
  • 1
    \$\begingroup\$ Once all clocks are stopped and no event is triggered anymore, simulation becomes infinitely fast. An arbitrary long simulated time can be used. \$\endgroup\$
    – Grabul
    Commented Sep 26, 2016 at 18:28
  • \$\begingroup\$ This answer would be improved by adding the std.env.stop method from @BrianDrummond comment above. \$\endgroup\$
    – scary_jeff
    Commented Sep 27, 2016 at 9:39
  • 1
    \$\begingroup\$ @scary_jeff I've updated the answer to include std.env.stop. Haven't seen this used "in the wild" yet, but I agree that this is the most elegant way to stop the simulator. \$\endgroup\$
    – Philippe
    Commented Sep 29, 2016 at 11:53

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