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This is a cascode current mirror. Assuming that all transistors are idential so that Iin equals Iout.

With the current, the gate to source voltage of all transistor are equal and it is Vgs.

Now I am confused about how Vgs of transistor Q4 is established by Iin or Iout.

For transitors Q1, Q3, they are diode connected transistors (feedback between input and output), so the current Iin is converted to the gate source voltage Vgs.

This is easy to understand. The diode connnected transistor is something like current to voltage converter here.

However, how the voltage Vgs of Q4 is established by the current In or Iout?

I don't see any kind of feedback here so that the output current Iin or Iout can be converted to its input voltage Vgs.

Could anyone explain what is happening here? How Q4 converts its current into the gate source voltage Vgs?

Thank you.

enter image description here

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Transistor Q4 is in a feedback loop as well.

Fixed input current: The gate voltage of Q4 is fixed and set by Q1 and Q3. The transistor Q2 has also a fixed Vgs and acts as a current source. Since the currents through Q3 and Q4 are the same, Q3 and Q4 have the same gate-source voltage. The source of Q4 is at the same potential as the source of Q3. The feedback mechanism that sets Vgs of Q4 is the same as for a changing input current.

Changing input current: Any change of the input current changes the gate voltage of Q4 which results in a change of its source voltage. The feedback results from the output resistance of Q2. If Q4 lets more current pass than Q2 can sink, the drain voltage of Q2 goes up and reduces the gate-source voltage of Q4, which in turn reduces the current of Q4.

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  • \$\begingroup\$ Thanks. "if Q4 lets more current pass than Q2 can sink": is this only assumption and it never happens in reality? I think that because Q2 and Q4 are in series so they always have the same current. \$\endgroup\$ – anhnha Sep 28 '16 at 2:54
  • \$\begingroup\$ You have to consider the transient behavior. Assuming that the source potential of Q4 is fixed and the output voltage (drain of Q4) moves up. A higher current flows through Q4 because of CLM. This current charges the parasitic capacitors at the source node of Q4. The source node moves up and reduces the current through Q4. \$\endgroup\$ – Mario Sep 28 '16 at 5:10
  • \$\begingroup\$ Sorry but I think you misunderstood my question above. In your analysis, you said if Q4 lets more current pass than Q2 can sink", I would like to know if the "if" will never happen in reality, right? Also, for your comment above, what happen if there is no parasitic capacitors (let's assume that)? \$\endgroup\$ – anhnha Sep 28 '16 at 8:13
  • \$\begingroup\$ In case there are no parasitics the current would settle without delay. The current trough Q4 and Q2 will be the same, but it will either flow through rds2 or gm2. The source voltage of Q4 will adjust such that the current of Q2 can flow through Q4. rds2 acts as the feedback element. \$\endgroup\$ – Mario Sep 28 '16 at 12:53
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Q4 is not 'driven' by its VGS, it's a common gate stage that accepts an input current from Q2, and transfers it to its drain.

You can also view Q4 as a source follower, with its source voltage set by Vd Q3. Without Q4, as the Vout changed, the drain voltage of Q2 would change, and that, through its finite output impedance, would change the output current. Q4 substantially isolates Q2 drain from output voltage variations, meaning that Q2 maintains a constant output current despite Vout variations. Essentially, the output impedance is increased by the gain of Q4.

The advantage of Q3/Q4 is solely an increase in output impedance, not an improvement in transfer ratio, or ratio stability, or noise.

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  • \$\begingroup\$ Thanks. And why don't we increase output voltage swing by making W/L as large as possible? \$\endgroup\$ – anhnha Sep 28 '16 at 4:30

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