I am using Xilinx's CoolRunner-II series CPLD, and programming programmable logic for the first time.

I have to use few of flip-flops with asynchronous reset.

I wonder what is the difference between active low and active high reset in terms of implementation?


1 Answer 1


There are two main reason for active low

  1. An reset active low flip flop can be implemented with one less transistor than active high.
  2. Upon power up, It's easier to keep reset at a 0 voltage level, whereas if reset were active high, the system would be unstable until reset crosses the threshold to get a '1'.

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