The typical clock frequency mentioned in the datasheet is 8 MHz. I haven't used an ATMega but I expect the onboard ADC has a maximum rate of < 1Msps.
You could probably drop the frequency but then your scanning would be slow. The datasheet doesn't mention minimums/maximums, so I'd be wary of doing anything other than what it does mention (not a lot) without confirming with Rohm. Maybe there is a separate app note that covers this stuff.
Anyway, you would be best off with a flash ADC with parallel interface, and a uC fast enough to read it comfortably (say at least 20 MIPS, maybe with a parallel port peripheral/DMA)
The datasheet gives no info in the analogue output quality, but I wouldn't expect it to be great so an 8/10 bit ADC will probably be suitable.
Then it looks like a simple case of pulse the SP input, wait 65 cycles and read just after the negative edge for 144 cycles. You may need an inverter with a slight delay (low pass RC would probably do to trim) on the ADC clock if it samples on the rising edge and you are driving both ADC/Module from same output pin.