One of EE.SEs famous answers advocates to use local ground-planes or -nets on ICs that generate broadband noise on power rails (like microcontrollers) in order to reduce excitation of planes as patch antennas and to improve EMI properties. I know there is some controversy about splitting planes, but I would like to ask about a special aspect:

Is using a star layout in the supply-layer (Vdd-star with a ground pour around it) and leaving the adjacent ground-plane unbroken also effective in reducing excitation of ground? Will the placement of such a star point (on center or near border of plane) make a difference?

The thinking behind this: high frequency return currents will be confined to the area below the star and partially cancel each other. Each branch of the star (to be precise: its return current on GND) will excite the plane in a different mode, depending on length and orientation of the branch. I prefer this approach, because this way, signal traces (which have their own return currents) do not have to cross plane boundaries.

I know I can get quantitative answers on such questions for specific cases from FEM analysis, but, not having access to such a tool, I am more after a general rule of thumb.

(Because I reference another post by Olin Lathrop, it may become confusing what "original post" means. Please make clear what you are referring to).

  • \$\begingroup\$ "With a good ground plane and good local power decoupling, power planes are usually unnecessary.". A comment from the author of that post. \$\endgroup\$ – pipe Sep 26 '16 at 16:08
  • \$\begingroup\$ @pipe I added a common pro plane argument to the question. \$\endgroup\$ – Andreas Sep 26 '16 at 16:14
  • \$\begingroup\$ what is dI/dt on the strongest current path? \$\endgroup\$ – Tony Stewart Sunnyskyguy EE75 Sep 26 '16 at 23:31
  • \$\begingroup\$ @TonyStewart For a uC or a FPGA, that will depend on what the component is doing. Right now, I am sweeping through some datasheets, but it seems that noone gives worst case values for this. For the circuit I am working on, it may be simpler: It is a mixed RF/digital with 5 CMOS output drivers, for which i can estimate a risetime of 4-5ns from diagrams. I would assume that the drivers pull is dominant for this chip (it may, lets say, contain 1200 gates or less). \$\endgroup\$ – Andreas Sep 27 '16 at 8:41

I don't see any flaw in that post's logic. High frequency return currents will be confined to the area below the star point (the post refers to it as a local plane). I can't say anything about EMI cancelling each other but the reduced antenna length will definitely reduce it's gain.

That said, the author of that post repeatedly ignores the dangers of high speed design with this topology. By definition, if all the high frequency elements are isolated to the MCU, your high speed signals leaving the MCU will have terrible slew rates and likely fail eye diagram requirements. He admits that only close to DC signals will leave the plane.

As someone commented, there is no free lunch. There should be a an overall warning that this is only suitable for low speed. Simply put, if any of your communication signals require impedance control, avoid this topology.

  • \$\begingroup\$ I also read the "free lunch" comment and that is what triggered me to ask this question. Differential signalling will of course help, but is only feasible for few signals as it will increase footprint for the whole circuit. \$\endgroup\$ – Andreas Sep 27 '16 at 9:00
  • \$\begingroup\$ I think you misunderstand how I recommend the grounds are connected. Keeping the high frequency power currents local doesn't detract from high frequency signal performance. See the High Frequency Signals section of my answer. \$\endgroup\$ – Olin Lathrop Sep 27 '16 at 12:47
  • \$\begingroup\$ I will accept this answer as most "on topic", although I got valuable input from all three answers. I will change some of my designs to have a plane only where it is needed. \$\endgroup\$ – Andreas Sep 29 '16 at 14:08

It's not really clear what you are asking:

Is using a star layout in the Vdd-plane

Star and plane are mutually exclusive.

(with a ground pour around it)

So now you have star-connected Vdd but inside the ground plane?

and leaving the adjacent ground-plane unbroken

How is this possible when you've already introduced this Vdd star that the ground is poured "around"? That "breaks up" the ground plane, or at least leaves a significantly large island in it. Either way, you don't have a ground "plane" anymore. Your question makes no sense.

It seems you may be asking about distributing power in a star versus some other shape, like chained, or some arbitrary branching topology the auto-router came up with. I'll talk about that.

The first thing for good EMI performance is to have a good ground plane. All power feeds should be locally bypassed anyway. These short loops from the chip power pin, thru the bypass cap, and back into the chip ground pin carry the high frequency currents produced by the chip. For good overall EMI performance, these loops should be small, and this loop current should be off the main ground plane.

For small chips with single power and ground pins, place the bypass cap as close as possible across these two pins, and route the connections directly without going onto the main ground plane. This makes a better connection anyway since there are no vias in the loop. Then add a via to the main ground plane, preferably close to the ground pin of the chip.

For larger chips with multiple ground pins, connect all the ground pins to each other and the low side of all bypass caps, then connect that to the main ground at one point. This can be a local plane on a separate layer, but doesn't need to be. In most cases, a star configuration with the via to the main ground at the star point is plenty good enough. If the chip has a "main" ground pin, put the star and the main ground connection near that pin.

One exception to this is if the chip has separate "power" and "signal" ground pins. What I talk about above is for handling the significant high frequency power currents produced by the chip. This applies to the "power" pins. A separate "signal" ground pin is intended as a clean and/or high frequency reference to signals only. That should be connected to the main ground plane with its own via close to that pin. The intent is that currents thru this pin are returns for signals going to or coming from elsewhere, so they aren't local in the first place. This board-wide ground reference is one of the things the ground plane is for.

None of this directly addresses the issue, which is about board-wide power distribution. However, to understand the that issue, the grounding strategy first needs to be clear.

With power feeds locally bypassed as described above, the high frequency properties of the global power feed become less important. A side benefit of clean EMI design is that less demands are placed on the global power feed system. You can evaluate it without worrying about high frequency performance, because that is already addressed by the local bypassing.

So now the issue comes down to star versus daisy chain versus tree, or whatever, power distribution at low to medium frequencies. From a purely DC point of view, a star will be better, but so little that in most practical cases it doesn't matter.

There will be one point in the power distribution net that is well regulated. This is where the regulator takes its feedback signal from. Generally this is at the immediate output of the power supply or regulator chip. Everything after that will have a voltage drop proportional to the DC resistance from the regulated point and the current.

In a star topology, the star point can be the well-regulated point. That minimizes dependencies of a voltage drop caused by one device on all the others. If the traces are thin and long enough, and the devices draw enough power, then this is something to consider. However, in most ordinary cases, this isn't worth the additional routing constraint. Look up the DC resistance of let's say a 20 mil copper trace a few inches long. Now multiply that by the worst case current your microcontroller or whatever will draw. The result is the voltage drop at the micro relative to the power supply output. This is so little in most ordinary designs as to not matter. A few mV difference in power voltage between digital chips on a board isn't meaningful.

The answer is therefore that while a pure star is best for maintaining the least power drop at each point of use, this isn't worth the cost of the additional routing constraint and complexity for most ordinary designs. In either case, it's not about EMI since that's dealt with by having good local bypassing at each point of use.

Of course it doesn't have to be all one way or the other. I just did a 5" x 9" board with three microcontrollers and a bunch of other circuitry around them. This board also included a display with backlight that draws 300 mA from the 3.3 V supply. In this case I did run a separate trace directly from the 3.3 V power supply output to the backlight, but let the auto-router connect the various other 3.3 V use points via whatever circuitous path it dreamed up. Of course I specified that the 3.3 V feed lines needed to be wide enough to handle the current without dropping significant voltage. In this case 20 mil was good enough. The backlight takes more current than all the other devices combined.

High frequency signals

I see one of the other answers objects to this scheme for high frequency signals. I think the problem is that what I was recommending was misinterpreted.

High frequency signal between chips or subsystems will have their return currents run across the ground plane. That's one thing the ground plane is for. Fortunately, the higher frequency components of these signals will automatically follow in the ground plane directly beneath the signal traces, thereby minimizing the overall loop area. Sometimes physics works to your advantage.

This is one reason you want a ground plane, not just a bunch of connected ground points. With a plane, the return currents can take whatever path they want to, which happens to be the optimum path anyway. This also points out the metric of a good ground plane. Vias and sometimes short "jumpers" are holes in the ground plane. What you want to minimize isn't so much the number of these holes, but their largest dimension. With a bunch of separated little holes, the return currents can flow around them and still largely take their preferred path. With a few big holes in the ground plane, the return currents have to go more out of their way to get around the holes, thereby increasing overall signal loop area and the EMI that goes with that. Worst case, a large island in the ground plane acts like a slot antenna.

So back to high frequency signals and the local ground method. The local ground net is for containing the local high frequency loop currents. Return currents for external signals have to flow in/out of the local net. For high frequency signals, the connection from the local net to the main ground therefore needs to not have significant impedance. The way this is dealt with is by good placement of the via that connects the local ground to the main ground.

When the local to main ground via is next to the ground pin, then you get the best of both worlds. Note that if you weren't using a local ground net, you'd put a via next to the ground pin too. The return path for signals is the same either way. A local ground net doesn't detract from high frequency signal performance, since those signals take the same path with either design strategy.

The difference between the two design strategies is the path that the local high frequency power currents take. The local ground method keeps them off the global ground plane, keeping it from being a center-fed patch antenna. The signal ground currents go directly from the ground pin, thru a via, to the main ground either way.

Local ground nets allow for the same high frequency signal performance as connecting everything to the main ground with its own via.

  • \$\begingroup\$ My formulation was unclear, it should have been "Vdd layer". I usually use 4 layer buildup with GND-plane in upper internal and supply in bottom internal layer. The question is if I should use star layout in the supply layer and if that will also help with the GND layer resonance. I will try to edit my question, but do not have time to do so right now. \$\endgroup\$ – Andreas Sep 27 '16 at 12:52
  • \$\begingroup\$ For the record, your original post described a single point connection or what I would call a ground peninsula. Here I believe you mention multiple ground connections through micro vias. If that's so, then don't these vias allow the chip's switching noise on to the main ground? The separation between local and main ground is reduced. It seems to me that in this case, the only thing to do is provide as many low inductance paths to the bypass caps. Hence my feelings of no free lunch. \$\endgroup\$ – lm317 Sep 27 '16 at 19:01
  • \$\begingroup\$ I take this and Tony Stewarts answers as "no, not effective" and lm317's as "yes, may be effective". Your detailed answer also helped me understand why there is no return path issue, if the chip has only one ground or you can identify the best signal return current ground pin on the chip. I have a hard time to accept one of the answers, as am still not able to judge on the plane resonance issue. \$\endgroup\$ – Andreas Sep 27 '16 at 22:52
  • \$\begingroup\$ @lm3: I'm talking about a single point connection between the local ground and the main ground, preferably right next to the ground pin of the part when it has a single ground pin. This provides the same return path for external signals since either way you connect the ground pin to the ground plane with a via. The difference is the bottom of the bypass cap is connected locally. That keeps the high frequency power currents off the main ground. \$\endgroup\$ – Olin Lathrop Sep 28 '16 at 11:04
  • \$\begingroup\$ I guess I'm still not getting in. Could you describe how this would look for something like this? xilinx.com/support/documentation/package_specs/… \$\endgroup\$ – lm317 Sep 29 '16 at 15:31

Star shaped power Vdc does not affect Ground plane resonance. But it can reduce path lengths on Vdc. Inductance is determined by length/width ratio and Zo is determined by conductor width to ground plane gap ratio.

Power planes are useless if there is a large dI/dt contributor carelessly located on the board. It should be closest to the low ESR&ESL decoupled source input then LC decoupling distributed to the rest of the board by trace or via or choke inductance and ground plane referenced caps at chip.

Power planes are useful when the FET switched capacitance loads cause transient noise, when it is widely distributed with high power.

Some RF chips and hybrids may still require shields if the board dimensions are > 1/10 wavelength and ground planes become unintentional radiators.

The power trace inductance is always determined by aspect ratio, so a square Cu area is always the same, no matter how big or small and coupling capacitance can give the lowest ESR when the dielectric is thinnest. But these are special cases with large complex motherboards that need power planes.

When using multiple layers for grounds multiple vias per feedthru reduce the ~1nH ESL of the via when spectral bandwidth is large. More microvias are better than one large one and should be every 1/10th of a wavelength considering lambda for f=1/3Tr with rise time ,Tr. This is also common in >1GHz radio designs.

Stripline and microstrip layout methods lower track impedance and reduce stray coupling to nearby signals.( Many different methods).

So determine where is the largest dI/dt unintended radiator and highest impedance susceptible receiver and create ground guards to absorb stray capacitive and inductive currents to the ground plane. Use active guarding on signals to lower capacitance and EMI ingress.

Use bus bars when appropriate to feed high switched current loads. Use star or poured power Nets with the net as large as possible near the source of the regulator which is inturn near the power entry to the board. whose inputs are decoupled by series chokes or ferrite beads to minimize dI/dt.

There are near field effects of crosstalk and far field effects for EMI constraints. Both must be considered in any layout simultaneously

All gaps, slots and traces are considered as antenna for the signals they carry.


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