It's not really clear what you are asking:
Is using a star layout in the Vdd-plane
Star and plane are mutually exclusive.
(with a ground pour around it)
So now you have star-connected Vdd but inside the ground plane?
and leaving the adjacent ground-plane unbroken
How is this possible when you've already introduced this Vdd star that the ground is poured "around"? That "breaks up" the ground plane, or at least leaves a significantly large island in it. Either way, you don't have a ground "plane" anymore. Your question makes no sense.
It seems you may be asking about distributing power in a star versus some other shape, like chained, or some arbitrary branching topology the auto-router came up with. I'll talk about that.
The first thing for good EMI performance is to have a good ground plane. All power feeds should be locally bypassed anyway. These short loops from the chip power pin, thru the bypass cap, and back into the chip ground pin carry the high frequency currents produced by the chip. For good overall EMI performance, these loops should be small, and this loop current should be off the main ground plane.
For small chips with single power and ground pins, place the bypass cap as close as possible across these two pins, and route the connections directly without going onto the main ground plane. This makes a better connection anyway since there are no vias in the loop. Then add a via to the main ground plane, preferably close to the ground pin of the chip.
For larger chips with multiple ground pins, connect all the ground pins to each other and the low side of all bypass caps, then connect that to the main ground at one point. This can be a local plane on a separate layer, but doesn't need to be. In most cases, a star configuration with the via to the main ground at the star point is plenty good enough. If the chip has a "main" ground pin, put the star and the main ground connection near that pin.
One exception to this is if the chip has separate "power" and "signal" ground pins. What I talk about above is for handling the significant high frequency power currents produced by the chip. This applies to the "power" pins. A separate "signal" ground pin is intended as a clean and/or high frequency reference to signals only. That should be connected to the main ground plane with its own via close to that pin. The intent is that currents thru this pin are returns for signals going to or coming from elsewhere, so they aren't local in the first place. This board-wide ground reference is one of the things the ground plane is for.
None of this directly addresses the issue, which is about board-wide power distribution. However, to understand the that issue, the grounding strategy first needs to be clear.
With power feeds locally bypassed as described above, the high frequency properties of the global power feed become less important. A side benefit of clean EMI design is that less demands are placed on the global power feed system. You can evaluate it without worrying about high frequency performance, because that is already addressed by the local bypassing.
So now the issue comes down to star versus daisy chain versus tree, or whatever, power distribution at low to medium frequencies. From a purely DC point of view, a star will be better, but so little that in most practical cases it doesn't matter.
There will be one point in the power distribution net that is well regulated. This is where the regulator takes its feedback signal from. Generally this is at the immediate output of the power supply or regulator chip. Everything after that will have a voltage drop proportional to the DC resistance from the regulated point and the current.
In a star topology, the star point can be the well-regulated point. That minimizes dependencies of a voltage drop caused by one device on all the others. If the traces are thin and long enough, and the devices draw enough power, then this is something to consider. However, in most ordinary cases, this isn't worth the additional routing constraint. Look up the DC resistance of let's say a 20 mil copper trace a few inches long. Now multiply that by the worst case current your microcontroller or whatever will draw. The result is the voltage drop at the micro relative to the power supply output. This is so little in most ordinary designs as to not matter. A few mV difference in power voltage between digital chips on a board isn't meaningful.
The answer is therefore that while a pure star is best for maintaining the least power drop at each point of use, this isn't worth the cost of the additional routing constraint and complexity for most ordinary designs. In either case, it's not about EMI since that's dealt with by having good local bypassing at each point of use.
Of course it doesn't have to be all one way or the other. I just did a 5" x 9" board with three microcontrollers and a bunch of other circuitry around them. This board also included a display with backlight that draws 300 mA from the 3.3 V supply. In this case I did run a separate trace directly from the 3.3 V power supply output to the backlight, but let the auto-router connect the various other 3.3 V use points via whatever circuitous path it dreamed up. Of course I specified that the 3.3 V feed lines needed to be wide enough to handle the current without dropping significant voltage. In this case 20 mil was good enough. The backlight takes more current than all the other devices combined.
High frequency signals
I see one of the other answers objects to this scheme for high frequency signals. I think the problem is that what I was recommending was misinterpreted.
High frequency signal between chips or subsystems will have their return currents run across the ground plane. That's one thing the ground plane is for. Fortunately, the higher frequency components of these signals will automatically follow in the ground plane directly beneath the signal traces, thereby minimizing the overall loop area. Sometimes physics works to your advantage.
This is one reason you want a ground plane, not just a bunch of connected ground points. With a plane, the return currents can take whatever path they want to, which happens to be the optimum path anyway. This also points out the metric of a good ground plane. Vias and sometimes short "jumpers" are holes in the ground plane. What you want to minimize isn't so much the number of these holes, but their largest dimension. With a bunch of separated little holes, the return currents can flow around them and still largely take their preferred path. With a few big holes in the ground plane, the return currents have to go more out of their way to get around the holes, thereby increasing overall signal loop area and the EMI that goes with that. Worst case, a large island in the ground plane acts like a slot antenna.
So back to high frequency signals and the local ground method. The local ground net is for containing the local high frequency loop currents. Return currents for external signals have to flow in/out of the local net. For high frequency signals, the connection from the local net to the main ground therefore needs to not have significant impedance. The way this is dealt with is by good placement of the via that connects the local ground to the main ground.
When the local to main ground via is next to the ground pin, then you get the best of both worlds. Note that if you weren't using a local ground net, you'd put a via next to the ground pin too. The return path for signals is the same either way. A local ground net doesn't detract from high frequency signal performance, since those signals take the same path with either design strategy.
The difference between the two design strategies is the path that the local high frequency power currents take. The local ground method keeps them off the global ground plane, keeping it from being a center-fed patch antenna. The signal ground currents go directly from the ground pin, thru a via, to the main ground either way.
Local ground nets allow for the same high frequency signal performance as connecting everything to the main ground with its own via.