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When I try to synthesize my VHDL design (using Xilinx ISE Design Suite), I get the message:

WARNING:Cpld - The signal(s) 'e' are in combinatorial feedback loops.
   These signals may cause hazards/glitches. Apply the NOREDUCE parameter to the
   hazard reduction circuitry.
   Timing analysis of paths involving this node may be inaccurate or incomplete.

This is confusing as my design simply consists of a counter 'c' that increases on each clock tick and some signals that are derived from it in a way where I don't believe any loop can exist, to form an output signal. Here's the code:

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;

entity foo is
    port (
        CLK : in std_logic;
        A : out std_logic_vector(1 downto 0)
    );
end foo;

architecture foo_arch of foo is

signal b : unsigned(1 downto 0);
signal e : std_logic;
signal c : unsigned(1 downto 0) := "00";
begin
   process (CLK, c)
    begin
        if rising_edge(CLK) then
            c <= c + 1;
        end if;
    end process;

    b <= c(1 downto 0) - 1;
    e <= '1' when b(1 downto 0) = 0 else '0';
    A <= std_logic_vector(b(1 downto 0)) when e = '1' else "ZZ";
end foo_arch;

So you can see

  • b is derived from c
  • e is derived from b
  • A (the output) is derived from b and e

What's the problem? Am I going crazy? Am I doing something incredibly stupid or is the synthesizer playing games with me?

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  • \$\begingroup\$ Maybe you do something strange in your testbench? \$\endgroup\$ – Vladimir Cravero Sep 27 '16 at 12:48
  • \$\begingroup\$ @VladimirCravero : the only relevant "something strange" would be to synthesise it, since this is a synthesis error... \$\endgroup\$ – Brian Drummond Sep 27 '16 at 12:52
  • \$\begingroup\$ Can you look at the synthesized circuit? This is probably some optimization that introduces a loop somewhere. \$\endgroup\$ – user110971 Sep 27 '16 at 15:32
  • 2
    \$\begingroup\$ c isn't needed in the process sensitivity list. What happens if your remove it? \$\endgroup\$ – user8352 Sep 27 '16 at 18:45
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Nice self-contained example and I agree with your analysis ... you are going crazy. No, wait ... in the good old days I'd be submitting this as a probable bug on Webcase. Now, you can try asking for comments from Xilinx staff on their own forum.

One not-too-hygienic construct : initialising c to "00" in the declaration is normally supported by Xilinx synthesis tools but possibly not for all architectures : I'd suggest adding a Reset input and assigning c <= "00"; in an if Reset clause, in case XST isn't obeying the initial value here and thus can't infer an initial state.

Other things to try

  • for some target devices, XST uses one VHDL parser with one set of bugs, for other target devices it uses a different parser. You can switch between parsers (possibly not for all targets) by setting the "Use New Parser - Yes" tick box (under Synthesis / Properties / Advanced View").
  • Vivado appears to have yet another VHDL parser you could try.
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It seems this is a bug in the Xilinx ISE VHDL synthesis tool. I was able to work around it by interposing a D-type flip-flop in the e signal. This delays the signal by one clock cycle, but, fortunately, it does not matter in my application.

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The warning arises because the order in which the signals b,e,A are assigned to is not defined. Under synthesis you are likely to get glitches with this circuit due to the differing delays. This is a warning because a subsequent circuit cannot rely on the dependencies between these signals beeing in a particular order. Without knowing what you are using this I don't know if it is correct or not.

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  • \$\begingroup\$ I have to disagree. I now believe the code is okay and it's just a bug in the synthesis tool. I don't see why there should be any glitches - there is no circular dependency between b, e, A, they all well defined. \$\endgroup\$ – Jiri Svoboda Aug 7 '17 at 11:14

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