When I try to synthesize my VHDL design (using Xilinx ISE Design Suite), I get the message:
WARNING:Cpld - The signal(s) 'e' are in combinatorial feedback loops. These signals may cause hazards/glitches. Apply the NOREDUCE parameter to the hazard reduction circuitry. Timing analysis of paths involving this node may be inaccurate or incomplete.
This is confusing as my design simply consists of a counter 'c' that increases on each clock tick and some signals that are derived from it in a way where I don't believe any loop can exist, to form an output signal. Here's the code:
library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; entity foo is port ( CLK : in std_logic; A : out std_logic_vector(1 downto 0) ); end foo; architecture foo_arch of foo is signal b : unsigned(1 downto 0); signal e : std_logic; signal c : unsigned(1 downto 0) := "00"; begin process (CLK, c) begin if rising_edge(CLK) then c <= c + 1; end if; end process; b <= c(1 downto 0) - 1; e <= '1' when b(1 downto 0) = 0 else '0'; A <= std_logic_vector(b(1 downto 0)) when e = '1' else "ZZ"; end foo_arch;
So you can see
- b is derived from c
- e is derived from b
- A (the output) is derived from b and e
What's the problem? Am I going crazy? Am I doing something incredibly stupid or is the synthesizer playing games with me?