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I have recently coded a filter in VHDL to be synthesized for an FPGA and I did it using the conventional method where you first design the finite state machine(FSM) and then implement it in your code. But I realized that when I reduced the number of states in the FSM by combining a few states, the filter worked much faster. So, in an attempt to maximize the speed of computation, if I just write the entire filter inside a process so that all the statements get executed sequentially, will it affect the computation in any way?

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  • \$\begingroup\$ What is your implementation? If you do it in a single process you are going to slow it way down for any but the smallest filters. A pipelined filter will get you a new sample every clock cycle. By that I mean multiplier stage followed by parallel added stages. \$\endgroup\$
    – user110971
    Commented Sep 27, 2016 at 15:48
  • \$\begingroup\$ Among things that depends on is if you want to use a lot of logic to calculate all your taps/operations in parallel, or if your sample rate is slow enough compared to possible FPGA clock rates that you want to save resources by time-multiplexing the same computational resources to calculate different taps/operations. \$\endgroup\$ Commented Sep 27, 2016 at 15:48

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Depends on how you want to build your filter. The real questions are these: what sample rate do you need, and how long is your filter? If your sample rate is low, then you can get away with an FSM driven design that can use many clock cycles to produce each output sample. It's certainly a good idea to make the FSM as efficient as possible, though. No sense on wasting extra cycles doing nothing, though it may make sense to do some pipelining so you can run at a high clock speed and get timing closure more easily. If your sample rate is high, then you can't spare the clock cycles and will have to implement more parallelism, probably in the form of some sort of pipelining. If your sample rate is so high that you need to process multiple samples on each clock cycle, then you need to do some pretty careful pipelined design.

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Ultimately when writing HDL (whether VHDL or verilog) you have to remember that you are writing code as a way of desinging hardware.

Your synthisis tool will often give you tools that let your view what it has done with your code at different stages in the processing. In quartus for example you can find these under "tools -> netlist viewers". These (especially the "rtl viewer") can be very handy for getting a feel for how code turns into hardware.

Designing hardware is a game of tradeoffs.

A state machine lets you reuse the same logic blocks for different things (or the same thing with different inputs, for example in a filter your state machine might use a single multiplier to multiply the input data item by all the different filter taps) but comes at the cost of throughput. The throughput is limited as the state machine has to work through different states for each data item.

A combinatorial design gives you results "immediately" but can create timing problems. When you write multiple processing steps in sequence in a process what happens in synthsis is that each of those steps becomes part of a chain of combinatorial logic with the final values of the variables being stored on in registers for use in the next iteration of the process.

A pipelined design can give high throughput and run at high clock speeds but typically requires the most logic and is the most mind bending to work with.

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Actualy a filter does only consist of delay, sum and gain operations and could be implemented as a simple sequential circuit which means that a process is appropriate to describe it.

e.g. consider this IIR-Filter

IIR-Filter (Wikipedia)

However it will require more expensive hardware resources (multipliers). If you implement the filter with a FSM you will be able to use the same multiplier for all gain operations.

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