Residual Power in Decoupling Capacitors

Question

I'm working on a battery powered prototype and have discovered an annoying bug. When power is removed from the device by disconnecting the battery, the voltage on the 5V power rail will decay fairly quickly to around 2V but then will decay much slower. In fact, it will stay between 2V and 1V for around 30 seconds. If the device is restarted during that time (i.e. the battery is reconnected), one of the chips will go into a bad state and the device will malfunction. This is especially annoying because this is precisely how most people power-cycle the device.

I figure that there is still residual charge being stored in the decoupling capacitors on the 5V power rail, which is causing the device to sit in this range for a while until parasitic resistances slowly drain the capacitors. Could this be correct?

If so, is there a generally accepted way to best discharge those decoupling capacitors?

Answer 1

The situation you described is very typical for devices with low-power CMOS ICs. This is called "brown-out" conditions.

One simple solution is to add so-called "bleeding resistors" to power rails that cause the trouble. But in this case you will waste some power during normal operations, which might be prohibitive from battery life standpoint.

More expensive solution (used in portable electronics/laptops) is to use active circuits (typically FET transistors) on power rails. The transistors are controlled by a voltage monitor, which turns the FETs on when some main voltage rail drops below certain limit, and the FETs discharge the rails quickly.

Some voltage regulator ICs have a built-in "auto-discharge" circuitry.

In many cases it is sufficient to provide a robust hardware reset to CMOS IC after the brown-out condition, if IC has a well designed hardware RESET which overrides any residual "bad" states after Vdd is restored.

Answer 2

revised....

On my PC I know if I press the power down, it will not reset all the circuits unless I wait 20 seconds or press the reset switch which presents a load to decay the charge faster in <1 second. Often a reset is detected by the positive change in voltage and if not sufficiently decayed, it cannot produce a positive reset when the cap is still charged with a pull down resistor. Although it is not destructive like you indicated in your situation, It prevents my full power on reset (POR) function.

But let's examine your real problem with a potential scenario.

"one of the chips will go into a bad state and the device will malfunction"

With LDO's and multiple supply voltages power sequencing can be is important to prevent CMOS latchup.

This can occur say when a logic chip powered perhaps by an LDO which all have common collector or drain type pullup regulators. Say the output is still holding a charge to activate a logic chip which interfaces with another chip which is powered by say 5V. Even if it accepts 3V logic but cannot accept inputs > 0.7V above the supply rail otherwise it biases a substrate SCR latch and causes the chip to short circuit when the 5V supply power is reconnected.

Although this is hypothetically true, it may not be the user's exact scenario.

Such a problem is usually handled by putting a Schottky diode in reverse across the LDO to not only protect the LDO but pull down by the output within a diode drop to prevent latchup on other interface chips using the higher input rail.