0
\$\begingroup\$

In my project, this section is faulty.

I'm doing a bit-banging operation with shift registers and I'm trying to make shift register data reset after 15 bits are shifted out from the micro controller. I connected the CLR lines of both 74HC164's in my project to pin 4 of the 74HC02 shown here. I know I could have used inverters but nor gates were what I had.

As I test, I notice at least a few times the reset operation on the 4024 not working. I verified this by temporarily connecting an LED from each output (one at a time) to ground through a 180 ohm resistor. Power supply is 5VDC.

I did try adding 1K pull-up resistors to the clock, reset and pin 5 of the nor gate and that did not help.

The purpose of this particular circuit is to reset the counter and shift registers (shift registers not shown) every 16 clock pulses made to the 4024.

Why is my 4024 behaving so strangely and how can I fix this?

circuit

\$\endgroup\$
5
  • 4
    \$\begingroup\$ INMHO this is a typical race condition. Reset pulse duration will depend on propagation thru IC3B, IC3C and 4024 internal circuitry from RES to Qn. This pulsewidth may be too short to reliably reset all the 4024 flip-flops and/or external shifters. This should definitevily turned into a syncronous machine. Otherwise you should try to lengthen reset pulsewidth. Sometimes a ballparking solution could be adding a small (10s pF range)capacitor across reset network. Not a very reliable nor repeatable way though. \$\endgroup\$
    – carloc
    Nov 27, 2016 at 11:24
  • \$\begingroup\$ Agree with @carloc. This is a poor asynchronous design with unpredictable reset pulse width. A reliable enough hack might be to put a series R on pin 10 of 74HC02 and add a small cap to RES input of 4024 to generate a longer reset pulse. The best fix would be as he said to turn it into a synchronous state machine design. \$\endgroup\$ Dec 28, 2016 at 8:17
  • \$\begingroup\$ @VincePatron, did you mean 'synchronous machine' as carloc suggested or actually a synchronous state machine? This would just be a synchronous design for a logic sequencer, wouldn't it, not an FSM. \$\endgroup\$
    – TonyM
    Mar 3, 2017 at 23:37
  • \$\begingroup\$ You did not specfy if a decoupling capacitor is used. \$\endgroup\$
    – Antonio51
    Dec 16, 2022 at 13:57
  • \$\begingroup\$ reset after 15 bits are shifted Whatever the relation between bits and clk to the 4024, starting from 0 the latter will need a 16th clk edge to assert Q5 . \$\endgroup\$
    – greybeard
    Apr 15, 2023 at 19:57

4 Answers 4

2
\$\begingroup\$

From Renesas document for CD4024, the minimum reset pulse width at 5V (@25°C) is 200ns. As has been pointed out by Carloc and Dwayne Reid, the generated reset signal by your circuit was way too brief to be registered by the binary ripple counter as proper reset. As Q5 goes high, the reset circuit triggers the reset pin to high. This causes CD4024 to initiate the clearing of all Qx output. However, individual Qx might not be cleared at the same time. So there can be 2 scenarios:

  1. If all the other Qx are cleared before Q5 is cleared, then as Q5 goes low, the reset signal goes low (deactivated) and everything is fine and dandy
  2. If Q5 is cleared before any other Qx are cleared, then as Q5 goes low, the reset signal goes low (deactivated) causing CD4024 to not clear those Qx that were not successfully cleared

The minimum reset pulse width is to avoid the undesirable scenario 2. This is the period needed to guarantee all Qx outputs are cleared to zero.

Dwayne Reid offered a reset circuit using an RC filter to lengthen the pulse width. However, this solution requires the RC time constant to be small enough such that the reset pulse width does not exceed the CLK clock period. Otherwise the counter will miss the next clock signal. A better solution is to use synchronous reset circuit as advised by Vince Patron.

Here is one such circuit: enter image description here

The idea is to activate the reset signal (high) for half the clock cycle, i.e. the RESET goes high (activated) when CLK and Q5 go low and high, respectively. And it remains high even Q5 instantly goes low as the result of the reset. The RESET only goes low (deactivated) when CLK goes high after half the cycle. This will give enough time for the CD4042 to properly reset (clear all its outputs Qx) before the RESET signal is deactivated. The only thing you need to ensure is that the clock period is not smaller than twice the minimum reset pulse width. For CD4024, the clock period should be >400ns at 5V (@25°C). If you use 74HC4024, then the clock period should be >40ns at 4.5V (@25°C).

\$\endgroup\$
1
\$\begingroup\$

As was mentioned by Carloc in the comments, the behavior that you are seeing is most likely caused by a race condition. The flip-flop that drives output Q5 is resetting faster than the other flip-flops.

The easiest way to fix this problem is to increase the width of the reset pulse. The NOR gates that you use to create the reset pulse can easily be configured to be a monostable timer which will deliver a fixed-width pulse when triggered.

Adjust the values of R1 & C1 for your desired reset pulse width.

schematic

simulate this circuit – Schematic created using CircuitLab

\$\endgroup\$
0
\$\begingroup\$
  • 74HC4024 clocks use negative edge and positive Reset (not shown on your schematic)
  • 74HC164 clocks use positive edge with negative Reset

  • This should count 1/2 after the shift register is clocked and reset after the - 16th bit when you only have 15 bits. Is that what where you went wrong??

    • How many clock pulses did you send?
  • Also 74HC4024 counters should be labeled Q0 to Q6 ( 7 bit counter ) although you have the Q1 as the correct pin for Q0, the first binary output.

\$\endgroup\$
10
  • \$\begingroup\$ mine is a CMOS 4024 (not HC series) for the counter. I intentionally have 15 bits as code for an 8K ram (13 bits for address, 1 bit for read/write control, and 1 to enable ram) \$\endgroup\$
    – user116345
    Sep 28, 2016 at 2:11
  • \$\begingroup\$ I want to add that the pulses are coming from the AT89C4051 microcontroller with an 11.0592Mhz crystal connected to it. This gives me a maximum pin pulse speed of about 1Mhz (921,583 times per second). Looking at the data sheet indicates to me that the maximum operating frequency of the cmos 4024 is 3.5Mhz. Also, my PCB is fine and everything is physically connected according to schematic, so I can't see it being a hardware issue unless I need different value pull-up or even pull-down resistors. \$\endgroup\$
    – user116345
    Sep 28, 2016 at 2:25
  • \$\begingroup\$ If the signal is more than 6" or so I hope you are using twisted pair or low impedance pair. \$\endgroup\$ Sep 28, 2016 at 2:51
  • \$\begingroup\$ The length of each track on the PCB is less than 1 inch long and the width of each track is 0.28mm. I also use a ground plane. \$\endgroup\$
    – user116345
    Sep 28, 2016 at 3:07
  • 4
    \$\begingroup\$ then slow down the rate and test it \$\endgroup\$ Sep 28, 2016 at 12:07
-1
\$\begingroup\$

I don't know if this helps, or is too simple. But it looks like the transition time of the 74HC02 is 20 to 40nsec (if I'm reading the specs correctly), but the minimum reset pulse width of the 4024 at 5V is 200nsec

\$\endgroup\$
2
  • \$\begingroup\$ After a quick 2nd thought I am not reading the 74HC02 specs (operation) correctly. Its pin 10 goes high and stays there until the 4024 output changes state and that wont be until the RESET changes it. My 1st answer at best took up otherwise valuable space. Sorry. \$\endgroup\$
    – RodB
    Feb 22, 2019 at 20:06
  • 3
    \$\begingroup\$ please edit your answer, rather than commenting. \$\endgroup\$
    – Daniel
    Feb 22, 2019 at 20:28

Your Answer

By clicking “Post Your Answer”, you agree to our terms of service and acknowledge you have read our privacy policy.