# How can I handle overflow or underflow in VHDL?

How can I handle overflow or underflow while implementing the following equation in VHDL for some iterations?

$$α= α(s) – max(αi)~~~~i ϵ (0,3)$$

If any of the $αi$'s become 0 or negative, the resultant normalized $α$ becomes negative and in this way while moving ahead we get $α$ a negative large value so question is how to handle this overflow?

1. Get the arithmetic correct before moving to hardware. Either in higher level VHDL for simulation, or in Matlab/Ada/Python/etc before moving to VHDL.
2. At this level, detect and handle overflows EXPLICITLY, i.e. not using accidental characteristics of the arithmetic in your chosen language. Verify this explicit model against a full resolution model (e.g. using double precision floating point) to make sure it delivers identical results, or results with acceptably low (rounding) error.
Three reasons I like Ada for this are:
(a) it supports custom fixed point types as first class citizens
(b) it raises exceptions for range errors, overflows, etc so I have confidence that I'm catching problems early. (NOTE : the gcc Ada compiler needs some flags set to do this properly)
(c) commonality with VHDL makes translation between them a breeze.
3. FIX problems and verify that the answers are satisfactory. For example:
(a) verify that over/underflows come in pairs and cancel out to give correct answers in some types of symmetric filter
(b) widen intermediate data types to handle overflows, then round and truncate into the required output data type
(c) Detect out-of-range values and saturate them to the range limits (in Ada, you can do this in an exception handler)

Once you know the mathematics is correct in detail, translate to synthesisable VHDL and verify the synthesisable version gives bit-identical results.

• Thanks for the answer. I will try it I hope it would be helpful. – user125007 Sep 29 '16 at 6:08