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After reading [Mike DeSimone]'s response regarding good decoupling and bypassing practices I kept wondering about distance between wires (wire = trace or net) .

[Mike DeSimone] comments that wires going to different nets should be as close as possible, but that wires that go to the same plane should be fairly appart.

If the currents in each of the parallel wires (I say "wire" to include both trace and via) are going in the same direction, then the mutual inductance adds to the self-inductance, increasing total inductance. If the currents in each wire are going in opposite directions, then the mutual inductance subtracts from the self-inductance, decreasing the total. This effect gets stronger as the distance between the wires goes down.

Therefore, a pair of wires going to the same plane should be far apart (rule of thumb: greater than twice the distance from surface to plane; assume the PCB thickness if you don't have your stackup figured out yet) to reduce total inductance. A pair of wires going to different planes, such as every example you have posted, should be as close together as possible.

··· Give the IC its own vias to power and ground, keeping opposing-net vias near each other and same-net vias farther apart ···

Now, all my designs have always been low frequency (<1MHz), but I recall having used, for example, more that one via to connect an MCU to a power plane. Or have used several vias to increase the maximum current of some traces that have to change layer, similar to this post. And I have placed them very close together (actually, as close as I could).

Could you please give me some insight on this matter? What is a good distance between vias or traces to avoid parasitic inductances?

I understand I can create a loop with two vias (perpendicular to my PCB), that is, if my vias are in series. But I fail to see how this can happen if they are in parallel or tie two unrelated components to the same net.

I have searched SE and googled, but found nothing useful to the matter of via clearance and the associated parasitics.


EDITS:

  • Fixed accidental cite to [Olin Lathrop] instead of [Mike DeSimone].
  • Changed question to include traces as well as vias (originally I only asked about vias).
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The more via's you use in parallel the less inductance you have. Each via can be modeled as an inductor with a few 10's of nH. If you really want to find the inductance closely there are calculations available on the internet that can help find what the inductance is based off of the dimensions of the via.

This is important if your designing for high speed (lets say 50Mhz+) as inductors with nH in conjunction with other components will form filters and limit the upper frequencies that the trace can carry. If your designing for low speed power planes, when a transistor switches in the microprocessor it will consume power from the plane and cause the voltage of the plane to dip below or above the intended value of the plane.

The power plane will recover as fast as it can get power from the source, if there is any parasitic inductance and or resistance it will limit the ability for the plane to 'recover' to its intended voltage.

Think of it this way:

schematic

simulate this circuit – Schematic created using CircuitLab

The processor is a dynamic load, it changes when transistors switch on and off. If the processor is using ~100uA when its sleeping and you wake it up and it then needs mA, this change can happen in the nanoseconds time frame. The inductance 'impedes' the power supplies ability for the current to get to the processor.

PCB components make a filter. Vias change the filter, if you have two it is going to have less impedance than one. Learn how to model PCB components as a circuit. Keep in mind that every trace, resistor, inductor and capacitor has values for capacitance, inductance and resistance. For example a resistor has nH's of inductance and pF's of capacitance. Two traces run together will have mutual inductance and capacitance between them, and also resistance. There are no ideal components in the real world.

A good rule of thumb is high frequency currents will travel the path of lowest inductance this could be through a component or even through the air (by turning traces into antennas). Keep in mind the capacitor also has parasitic inductance. If you place an inductor in between the power plane and the cap or between the ground plane and the capacitor, you will increase the inductance and you will reduce the capacitors 'ability' to function as an energy storage tank on short timescales. To negate this effect place two vias on the capacitors return path to ground.

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  • \$\begingroup\$ Indeed that is how I thought vias (and for that matter, traces) would behave at high frequencies. But then, why does the recommendation in the OP say the opposite? Is there any secondary effect I have not thought of? Why should I keep them at least twice the planar distance apart?. Also, thank you for all the details in your response :) \$\endgroup\$ – andresgongora Sep 29 '16 at 8:02
  • \$\begingroup\$ Because you also have to consider the parasitics of the whole circuit. Each trace has inductance and resistance. If you model the whole circuit pathway including the parasitic inductance of the capacitor you get some interesting effects at high frequencies. \$\endgroup\$ – laptop2d Sep 29 '16 at 15:39

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