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The 74HC series can do something like 20MHz while 74AUC can do something like maybe 600MHz. What I'm wondering is what sets these limitations. Why can't 74HC do more than 16-20MHz while 74AUC can and why can't the latter do even more? In the latter case, does it have to do with physical distances and conductors (e.g. capacitance and inductance) compared to how tightly packed CPU ICs are?

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  • \$\begingroup\$ Just imagine if you'd designed a circuit which depended on the timing characteristics of, say, a 74HC00 which has been available since the 1980s (maybe earlier), and then suddenly such chips weren't available any more because someone had gone and made them into 600 MHz-capable devices. \$\endgroup\$ – Andrew Morton Sep 28 '16 at 18:44
  • \$\begingroup\$ And why is the CD4000 series still so slow? Sometimes slower is better (eg. when you want to eliminate glitches and interference). Speed/power/voltage tradeoffs are also factors. CD4000 can run on 15V, which would cause prohibitive power consumption at 600MHz! \$\endgroup\$ – Bruce Abbott Sep 28 '16 at 19:03
  • \$\begingroup\$ I didn't ask why 74LS and 74HC are still available. I asked why faster chips aren't available. \$\endgroup\$ – Anthony Sep 28 '16 at 19:08
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    \$\begingroup\$ 74AUC may have '74' in the name, but as it has a maximum recommended operating voltage of 2.7V it's not really that close to the 74HC parts. Also toggle frequency of a FF is 'only' 350MHz at 2.5V supply (less at lower voltages). \$\endgroup\$ – Spehro Pefhany Sep 28 '16 at 19:10
  • \$\begingroup\$ @Sphero, you're just supoposed to use a ton of pull-up resistors! jk \$\endgroup\$ – Anthony Sep 28 '16 at 19:16
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As technology size decreases, wire resistance/capacitance cannot scale proportionally to the propagation delay of the now faster/smaller transistors. Because of that, the delay becomes largely wire dominated (as the transistors composing the gates shrink; both their input capacitance and output drive capabilities decrease).

So, there is a tradeoff between a faster transistor and the drive capabilities of the same transistor for a given load. When you consider that the most significant load for most digital gates is the wire capacitance and ESD protection in the following gates, you will realize that there is a point at which making the transistors smaller (faster and weaker) no longer decreases the delay in situ (because the load of the gate is dominated by wire and ESD resistance/capacitance of wires and ESD protection to the next gate).

CPU's can mitigate this because everything is integrated together with wires sized proportionally. Even so, the gate delay scaling is not being matched with interconnect delay scaling. Wire capacitance is reduced by making the wire smaller (shorter and/or thinner) and insulating it from nearby conductors. Making the wire thinner has the side effect of also increasing the wire resistance.

Once you go off-chip, the wire sizes connecting the individual ICs become prohibitively large (thickness and length). There is no point in making an IC which switches at 2GHz when it can practically only drive 2fF. There is no way to connect the ICs together without exceeding the maximum drive capabilities. As an example, a "long" wire in newer process technologies (7-22nm) is between 10-100um long (and perhaps 80nm thick by 120nm wide). You can not reasonably achieve this no matter how smart you are with the placement of your individual monolithic ICs.

interconnect vs technology

And I also agree with jonk, regarding ESD and output buffering.

As a numerical example about the output buffering, consider a practical current technology NAND gate has a delay of 25ps with an appropriate load, and an input slew of ~25ps.

Ignoring the delay to go through ESD pads/circuitry; this gate can only drive ~2-3fF. To buffer this up to an appropriate level at the output you may need many stages of buffer.

Each stage of buffer will have a delay of around ~20ps at a fanout of 4. So you can see that you very quickly lose the benefit of faster gates when you must buffer the output so much.

Lets just assume the input capacitance through the ESD protection + wire (the load which each gate must be able to drive) is around 130fF, which is probably very underestimated. Using fanout of ~4 for each stage you would need 2fF->8fF->16fF->32fF->128fF : 4 stages of buffering.

This increases the NAND 25ps delay to 105ps. And it is expected that the ESD protection at the next gate will also add considerable delay.

So, there is a balance between "using the fastest possible gate and buffering the output" and "using a slower gate which inherently (due to larger transistors) has more output drive, and thus requires less stages of output buffering". My guess is that this delay occurs around 1ns for general purpose logic gates.

CPU's which must interface with the external world get more return on their buffering investment (and hence still pursue smaller and smaller technologies) because rather than paying that cost between every single gate, they pay it once at each I/O port.

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  • \$\begingroup\$ Thanks, that's what I thought; makes complete sense. What is 2fF? \$\endgroup\$ – Anthony Sep 28 '16 at 19:12
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    \$\begingroup\$ Femtofarad, ok, got it. \$\endgroup\$ – Anthony Sep 28 '16 at 19:17
  • \$\begingroup\$ It is "femto Farades" , 1/1000th of pF. \$\endgroup\$ – Ale..chenski Sep 28 '16 at 19:18
  • \$\begingroup\$ Additionally I think you can get them a bit better than the top notch chips there are today, but there is simply no market that would need those chips for the price they would cost \$\endgroup\$ – PlasmaHH Sep 29 '16 at 9:25
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Going off-chip means that the output load is largely unknown, though there are specification limits. So driver transistors have to be very large and cannot be sized for a precisely-known load. This makes them slower (or requiring a more current drive which also requires larger support transistors), but the specifications for what they have to drive also makes the final specification about speed lower, too. If you want to drive a wide range of loads, you have to specify a slower speed for the device. (I suppose you could internally "re-specify" some of the speed rating, if you happen to know your own exact load. But then that would be you taking the risks. You'd be out of the chip's specifications, so the burden for functionality would be yours.)

Each input (and possibly output) also need protection from static and general handling. I think the manufacturers, for a while in my ancient memory, did ship parts without protection and added lots of "don't do this, don't do that, do this, do that" in the handling of parts to help make sure you didn't accidentally destroy them. Of course, people destroyed them, regularly. Then, as it become more feasible to add protection, most manufacturers did so. But those who didn't, and still kept all the notifications about handling their parts, found that their customers still wound up destroying parts and sending them back as "defective." The manufacturer couldn't argue well. So I think pretty much all of them have caved in and place protection on all the pins. (With still very rare exceptions where the protection itself interferes with the functional requirements.) This protection also adds capacitance and leakage and noise it slows things down.

I'm sure there are still more reasons. It's likely that the heating will be preferentially applied to the output drivers, so additional thermal range of operation for the drivers probably then suggests still more limits on specified speed. (But I haven't calculated any of that, so I'm offering it as a thought to consider.) Also, the packaging and chip carrier, themselves. But I think it does boil down to the fact that a packaged IC makes a range of specified assumptions about the "outside world" it will "experience." But a designer of one internal functional unit communicating between other, well-understood, internal functional units can be tailored exactly to its known environment. Different situations.

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  • \$\begingroup\$ That's also an interesting point. \$\endgroup\$ – Anthony Sep 28 '16 at 19:13
  • \$\begingroup\$ Some questionable assumptions, I could debate but wont . Potato's chips do meet all ESD specs, with higher Cin than some but spec 50 Ohm input terminators to meet some specs and have same RdsOn as ARM logic (25nom). They run slower hot, not faster like all CMOS., fine print says Airflow of 1m/s is recommended for frequencies above 133MHz , no doubt from dynamic losses with Cout \$\endgroup\$ – Sunnyskyguy EE75 Jan 12 '17 at 13:37
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The limitations are set by application space. The lecture about shrinking nodes is not really applicable here. "jonk" has it much better. If you need a logic gate switching above 500-600MHz (<2ps prop delay time), you will need to use smaller transistors. Smaller transistors cannot drive big loads/traces which are found on usual PCBs, and the package pin/pad capacitance and inductance already take a big chunk of this load. Input ESD protection is another thing, as "jonk" also noted. So in short, you cannot take a naked 32-nm gate and package it into plastic case, it will fail to drive its own parasitic I/O. (typical pin capacitance is 0.1-0.2pF, see TI note)

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  • \$\begingroup\$ You say that I got it wrong, then paraphrase what I said... This is your own quote: "The lecture about shrinking nodes is not really applicable here" ... "you will need to use smaller transistors. Smaller transistors cannot drive big loads/traces" ... ??? Shrinking nodes == smaller transistors \$\endgroup\$ – jbord39 Sep 28 '16 at 21:29
  • \$\begingroup\$ @jbord39, sorry if my wording was too harsh. Your response was focused on internal workings of Large-scale ICs, while the actual limitation is in making a reasonably handlable I/O ring. If you look at your diagram, you will see that even at 130nm the gate delay is in ps range, while available 74AUC gates are at 2ns range, at least two orders in magnitude. That's why I said "not really applicable". \$\endgroup\$ – Ale..chenski Sep 28 '16 at 21:51
  • \$\begingroup\$ Okay, that makes sense. But in my mind the two phenomenon are directly correlated. Even in the chart, the reason the wire delay is so small is because this is in a CPU. The 74AUC technology is most likely much larger than 130nm (I have looked and looked but cannot find the actual size in that series). Faster FET means smaller FET and smaller FET means less output drive. And the 2ps 74AUC -> 2ns in 130nm technology is just a further argument for the diminishing returns of using smaller FETs in monolithic packages because of the buffering required (essentially increasing gate delay). \$\endgroup\$ – jbord39 Sep 28 '16 at 22:09
  • \$\begingroup\$ I agree with @jbord39 , also RdsOn for potatochips is the same as ARM's 25 Ohm nom (Vol/Iol) Although 1m/s cooling is needed for dynamic losses is their tradeoff. 800ps rise time max @ 2pF load but their load is6pF for '74 series \$\endgroup\$ – Sunnyskyguy EE75 Jan 12 '17 at 13:54
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Depends where you look. Some companies make logic "rated" for 1GHz: http://www.potatosemi.com/potatosemiweb/product.html

However, as others have said, past a few dozen MHz, it doesn't make sense to use discrete logic devices, except in edge cases that the big companies don't (or can't) always cater to.

edit: I feel a need to clarify that I've never used or worked with Potato Semiconductor Corp, I just know they're a company that exists, and GHz logic is their claim.

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    \$\begingroup\$ @user3470630 Potato Semiconductor Corporation? The name looks like a joke. Their web site looks like my grandmother designed it (with real pieces of approximative syntax inside). Their datasheets look like they're made in 10 minutes each, using MS Word. Overall, this gives a strange feeling. At the bare minimum, they urgently need to set up a decent marketing department. \$\endgroup\$ – dim Sep 29 '16 at 8:32
  • \$\begingroup\$ The maximum operating frequency depends on the capacitive load, for instance 1.125 GHZ at 2 pF, 750 MHz at 5 pF and 350 MHz at 15 pF. But the input capacity of a 74G00 is 4 pF typically. With only one input tied to an output, the maximum frequency is already below 1 GHz. Four inputs and we get only less than 350 MHz. But the datasheet looks good to me. \$\endgroup\$ – Uwe Sep 29 '16 at 14:56
  • \$\begingroup\$ @dim: I can't get over the name either. I burst out laughing everytime re-think about it \$\endgroup\$ – jbord39 Sep 29 '16 at 22:20
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    \$\begingroup\$ @DmitryGrigoryev It seems you can buy directly from their website. Actually, I don't think it's fake. A fake company would make more money, and in a simpler way, by selling counterfeit Atmel chips, or whatever. It's just that their communication/marketing skills are... Well... Can't find an appropriate word, but you know what I mean. \$\endgroup\$ – dim Oct 1 '16 at 6:44
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    \$\begingroup\$ @dim: their marketing skills are potato \$\endgroup\$ – jbord39 Oct 12 '16 at 0:20
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(2nd reply)

The 74HC series can do something like 20MHz while 74AUC can do something like maybe 600MHz. What I'm wondering is what sets these limitations.

  • basically smaller lithography , smaller loads, lower Vgs, low Ron
  • For Potato brand PO74', also higher Vss, smaller test loads, forced air cooling 1m/s in fine print permits higher f max, differential internal logic, specmanship
  • smaller inputs, drivers, ESD diodes

Why can't 74HC do more than 16-20MHz while 74AUC can and why can't the latter do even more? In the latter case, does it have to do with physical distances and conductors (e.g. capacitance and inductance) compared to how tightly packed CPU ICs are?

  • PO74G04A \$t_{pd}= \ \ \ 1.4 \ ns_{ max} \ \ _{with \ load= \ \ 15pF//1kΩ @ 3.3V } \$

    • \$f_{max}= 270MHz @ 15pF, 1125MHz @ 2pF\ \ \ \ \ \ (smaller \ spud \ load)\$
  • 74AUC16240 \$t_{pd}= \ \ \ 2 \ ns_{ max} \ \ _{with \ load= \ \ 30pF//1kΩ @ 1.8V }\$

  • 74HC7540 \$ \ \ \ t_{pd}= 120 \ ns_{{max}} {{@2V, 20 \ ns_{max}@6V } \ \ _{with \ load= \ \ 50pF//1kΩ} }\$

    • 74HC244 \$ \ \ \ \ t_{pd} \ = \ \ 11 \ ns_{typ}\ \ \ \ \ \$ @6Vss 50pF

    • lower Vgs

      • '74AUC' runs 0.8V to 2.7V designed for 1.8 or 2.5V
      • '74HC' runs 2V to 6V , must use higher Vgs
    • differences in Cin

      • 'PO74G' Cin = 4pF
      • '74AUC' Cin = 4.5pF
      • '74HC' Cin = 10pF
    • ESD protection

    • '74HC' '74AU' varies from 1~2kV HBM
    • PO74G04A potato chip meets 5kV HBM A114-A

Historical RdsOn changes in CMOS logic families

300Ω ~1KΩ for 15V~5V Vcc (CD4xxx)
50~100Ω for 5V Logic 74HCxxx
33~55Ω for 3~5V Logic (74LVxxx)
22~66Ω for 3.6V~2.3V logic (74ALVCxxx)
25Ω nom. ARM logic
66Ω MAX @Vss=2.3 for 0.7~2.7V logic SN74AUC2G04 
    0.5typ 1.2max ns for CL=15pF RL=500
    0.7typ 1.5max ns for CL=30pF RL=500

(1st reply)

Let's me add a different perspective to the excellent answers using first order RC effects. I assume the reader is aware of lumped element and transmission line effects.

Historically, since CMOS was produced, they wanted to supply a wide range Vss limits but avoid Shoot-Thru during transition, so RdsOn had to be limited. This also limited rise time and transition frequency.

  • As technology improved with small lithography and smaller RdsOn, while the Cout actually increases but they are able to reduce Cin since it acts as a buffer. They had to limit Vss due to thermal effects and risk of Shoot-Thru with very low RdsOn.
  • This is still the challenge seen in half-Bridge PWM motor drivers and SMPS

schematic

simulate this circuit – Schematic created using CircuitLab

RdsOn (approx = Vol/Iol ) typ ~ worst case

  • 300Ω ~1KΩ for 15V~5V Vcc (CD4xxx)
  • 50~100Ω for 5V Logic 74HCxxx
  • 33~55Ω for 3~5V Logic (74LVxxx)
  • 22~66Ω for 3.6V~2.3V logic (74ALVCxxx)
  • 25Ω nom. ARM logic

    • R source * C load ≈ T Rise Time to 60%V
  • limiting factor e.g. 25Ω*30 pF = T@60% = 750ns
  • but actual thresholds may be 50% or +/-25%

Conclusion:

Without perfect transmission line controlled impedances, CMOS switched voltages can never approach the speeds possible with Current mode Differential Logic.

Although this adds a lot of complexity and cost, so industry instead goes with smaller Litho inside one package to limit the stray capacitance and interconnect speed can be slower.

Then parallel CPU's is more power efficient than fast CPU speeds. This is due to the power dissipated during IR transition times determined by RdsOnC to achieve higher speeds.

If you examine all MOSFET datasheets you will find RdsOn is inverse with Ciss within any family or technology.

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