Suppose you have this circuit diagram,enter image description here I do not understand my professor's lecture. My professor said that AB equal 10 is restricted as when it is changed to 01, it would cause q to be either 1 or 0 depending on the delay of the circuit elements. Could you clarify how such thing happen. After consulting the textbook, this is what it says:

"AB = 01 is a hold input combination, AB = 00 and 10 are reset input combinations, and AB = 11 is a set input combination. This is reset dominant latch where S = A and R = B'. P = Q' + B'. In each stable state P = Q' even for the input combination AB = 10 (SR = 11) so P is usable as Q'.
Allowing the input combination AB = 10 (SR = 11) would result in unreliable operation if both A and B could change at the same time, i.e., change to AB = 01 (SR = 00), because the latch could end up in either state 0 or 1 depending upon the delays in the circuit."

  • \$\begingroup\$ A logic signal consists of more than one door is passed with delay. When you compared with source logic you got an condition. Every IC got transition time (mean delay), maybe microseconds, nanoseconds, picoseconds etc. Shortly trick Compare with results before using logic signal, detect rising/falling edge, check pattern, make an output... But be careful on rising/falling,logic signal duty always needdelay_logic_duty > transition time. \$\endgroup\$ – dsgdfg May 15 '17 at 7:31

This transition is illegal and simultaneous changing inputs causes a "race condition" or "metastable". If you recognize the dual gates as an SR LATCH ( or simple asynchronous Set/Reset Flipflop ) with active low inputs then a negative glitch may cause a different output result. enter image description here

In general it depends on rise time, prop delay, setup, hold time of any device.

  • \$\begingroup\$ Can you please explain more how the glitch would happen? Thanks! \$\endgroup\$ – Derpson Sep 29 '16 at 13:40
  • \$\begingroup\$ If A going low is slower than B going high both inputs are high momentarily and NAND out is low which forces a SET on Q. Otherwsie if B is slower there is no glitch. Generally these are prevented by gating input signals with a clock for synchronous changes and a forced race or only changing one input at a time by stagger clocks driving A,B. or some other arrangement all together. These are "asynchronous operations" so race conditions must be avoided here. These delays can occur due to trace capacitance (rise time) and length prop delay in nanoseconds). \$\endgroup\$ – Tony Stewart EE75 Sep 29 '16 at 13:53
  • \$\begingroup\$ I think it is a lot clearer to refer to that as an SR latch, not SR flip flop. An SR flip flop, which does exist, is two gated SR latches back to back with opposite polarity clocks (master-slave): play-hookey.com/digital/sequential/rs_nand_flip-flop.html \$\endgroup\$ – jbord39 Oct 29 '16 at 15:34
  • \$\begingroup\$ I agree , my slack terminology, corrected, although in theory , registers, memory state logic , flip flops and latches are synonyms with specific use making differences \$\endgroup\$ – Tony Stewart EE75 Oct 29 '16 at 16:59

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