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I am little bit confused about the requirements of USB 2.0 high-speed.

USB 2.0. high-speed maximum transfer rate is 480 Mbit/s. So from my understanding to fully utilize this data rate one should use IC(uC or FPGA) with frequency at least 480 MHz.

But for example STM32 F4 series microcontroller provide USB 2.0 high-speed support, though the maximum frequency they run on is 180 MHz.
Also Atmel SAM3U supports high-speed USB, despite absolute maximum frequency of 192 MHz.
How is that?

For Atmel I noticed they have additional clock of 480 MHz just for USB. This is even more confusing, since if microcontroller is capable only of 192 MHz -how it should communicate with internal USB periheral that runs on 480 MHz?

For STM32 it is also weird, in their CubeMX software it seems they run USB from 48 MHz clock. Searching datasheet, only mention I found was

Bit 15 PHYLPCS:
PHY Low-power clock select This bit selects either 480 MHz or 48 MHz (low-power) PHY mode. In FS and LS modes, the PHY can usually operate on a 48 MHz clock to save power.
0: 480 MHz internal PLL clock
1: 48 MHz external clock
In 480 MHz mode, the UTMI interface operates at either 60 or 30 MHz, depending on whether the 8- or 16-bit data width is selected. In 48 MHz mode, the UTMI interface operates at 48 MHz in FS and LS modes.

So I suppose it uses 48 MHz clock to generate 480 MHz through PLL. But again - if microcontroller itself can only go up to 180 MHz - what is the point of 480 MHz USB?

FPGAs are even more confusing(many run below 480 MHz), but I haven't done much research on FPGA yet, so I will not ask anything(but if you can give some advice/educate about FPGA - you are welcome, I am interested).

The question is - if we use 180 MHz microcontroller and want to transfer data with 480 MHz usb peripheral - how does it match the frequency? What is the process?

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  • \$\begingroup\$ Processors deal with more than a single bit at a time. \$\endgroup\$ – R Drast Sep 29 '16 at 16:00
  • \$\begingroup\$ Don't mix the processor clock and the transceiver clock. \$\endgroup\$ – Eugene Sh. Sep 29 '16 at 16:08
  • \$\begingroup\$ OK, answer by Ali Chen makes it clear. \$\endgroup\$ – ScienceSamovar Sep 29 '16 at 16:11
  • \$\begingroup\$ Also please be aware that data processing is not always done by CPU, there is DMA and other staff. An example is that an USB3.0 flash drive cotroller only contain a 8051CPU and still can deal with 5Gbps speed. \$\endgroup\$ – jw_ Nov 11 '19 at 4:40
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Please note that USB is 480M bits per second, while uPs have their data usually 8 or 32 bit wide. So the rate of system data transfer goes down to 60MHz or 15Mhz only. USB controllers use hardware access to uP memory (aka direct memory access, or "bus mastering") to transfer blocks of data between the system memory and USB PHY (Physical layer transceiver). The transfers are done in 8 or 16-bit parallel format, and the PHY performs parallel-to-serial conversion. The system usually has plenty of "elasticity" buffers (FIFOs) to provide coherent USB packets in full accords with specified data rates.

The rate of how fast a system can prepare the read/write memory buffers depends on overall processor throughput, so low-performing processors might not achieve maximum USB throughput.

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  • \$\begingroup\$ Am I understanding correctly: we put 32 bit in some USB register and USB PHY then sends them one by one? But then we need to match cycles also, so when 32nd bit is sent uC needs to put next 32 bits in the register. So we need to write to that register at a clock of 15 MHz to maintain stability. Did I get it? \$\endgroup\$ – ScienceSamovar Sep 29 '16 at 16:07
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    \$\begingroup\$ No, it is more complicated. System prepares a linked list of blocks with data it wants to transfer, and launches the operation on USB controller. The USB controller reads the list automatically and communicates entire data blocks to PHY, and performs all necessary USB protocol (forming request tokens and responding to/with ACks etc.) \$\endgroup\$ – Ale..chenski Sep 29 '16 at 16:11
  • \$\begingroup\$ I think I have better grasp on it now, thanks. I accepted the answer, I will investigate further by myself. If somebody wants to add something - feel free, I'll upvote. \$\endgroup\$ – ScienceSamovar Sep 29 '16 at 16:13
  • \$\begingroup\$ To my knowledge, every modern uP with USB host function adheres to Intel EHCI specifications, intel.com/content/dam/www/public/us/en/documents/… . Device implementations can differ. \$\endgroup\$ – Ale..chenski Sep 29 '16 at 16:16
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    \$\begingroup\$ Just to add a few notes, 480mbps, should be divided by 10 (since the data goes through an 8b/10b block on TX and 10b/8b on the RX side), which gives the maximum data bandwidth to 48MByte/second, which is about 11M access per second for a 32bit processor. \$\endgroup\$ – FarhadA Sep 30 '16 at 11:41

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