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I tinker with AVR, 6502 and z80 designs, just muck around really, nothing overly serious. But as a result I had a thought of an idea for a new chip.

Specifically a SoC built around a z80 core. But who would I talk to too even see if what I'm thinking is feasible? And if it is who would I talk to too, to get a price estimate to have the thing designed into a chip? Would the cost of doing something like this be prohibitively expensive?

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    \$\begingroup\$ Prepare a nice presentation with a business plan. Present it to investors. Get money from them. Open a start-up. Spend the money. Close the start-up. Profit! No need to make the chip, actually.. \$\endgroup\$ – Eugene Sh. Sep 30 '16 at 16:52
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    \$\begingroup\$ Why would you want to base anything around 1970s technology? \$\endgroup\$ – Chu Sep 30 '16 at 16:53
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    \$\begingroup\$ Look at this question. Some of the detail may well have changed since then though. Do you have a plan to license the z80 core which will work on your target process? electronics.stackexchange.com/questions/7042/… \$\endgroup\$ – Sean Houlihane Sep 30 '16 at 17:19
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    \$\begingroup\$ BTW @justin808 my very rough feasibility cost numbers would be $250k plus $50k for every peripheral you license rather than write. But I'm not sure what the market would be - why buy one of these rather than an 8051 or other 8bit design? \$\endgroup\$ – pjc50 Sep 30 '16 at 17:54
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    \$\begingroup\$ @Justin808 no MCU requires linux to run. You can program the ones I mentioned with some bare-metal system, eventually emulating an Atari or some other 8-bit machine. A simpler option for what you seem to need would be a FPGA. I'm quite sure some other people have implemented whole vintage systems on FPGAs already. Look at opencores.org. \$\endgroup\$ – dim lost faith in SE Sep 30 '16 at 20:13
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Almost anything along those lines is possible, and many are even economical if the volume is large enough. So a good first step would be to make sure you have an understanding of the size of the potential market for your idea and what price it might bear.

If I were in your situation, I would then talk to a trusted friend who works in the semiconductor design and/or fabrication business to see whether it's feasible and get an idea of costing. But I'm fortunate to know a few such people. If you don't, I'm sure you can find a suitable consultant and pay for a few hours of her time for an initial assessment. Be sure to have her sign an NDA protecting your potential IP, she might have a suitable template you can use so you don't necessarily need to engage a lawyer at this point.

You would ultimately end up either partnering with or becoming a fabless semiconductor manufacturer.

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It would be prohibitively expensive to get an ASIC made. In the order of a million dollars.

What you would generally do is develop the chip on an FPGA first to see if it would work without such costs. But to get it finally developed it's exceptionally expensive

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    \$\begingroup\$ This is a bit of an exaggeration. For small numbers of parts, its potentially quite a lot less - particularly on the older processes. \$\endgroup\$ – Sean Houlihane Sep 30 '16 at 17:14
  • \$\begingroup\$ +1 for bringing FPGA into play. Altera Hardcopy design flow was particular useful IMO. \$\endgroup\$ – Andreas Sep 30 '16 at 18:26
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Some things:

You will need to obtain a license for the z80 core. This would be in the form of soft or hard intellectual property (SIP or HIP). SIP is the RTL code. HIP would be it implemented in silicon for a particular technology node. There are more ambiguous in-between IP's as well (maybe the critical areas are hardened but the glue logic is provided only as RTL for you to synthesize).

Based on which of these avenues you choose to pursue, you would need: - SIP : You will need a synthesis engine to translate the RTL into gates, such as DC Synthesis. You will need access to full chip timing analyzers, such as Synopsys PrimeTime or ICC. - HIP: You will still need the timing engine but may be able to get away without the synthesis engine depending on how you build the circuits around the core.

Either way you will need a foundry willing to construct the chip, and a tool to run design rules checks on the layout, and to run schematic vs. layout (Virtuoso comes to mind).

In the SIP approach you can implement the core in whatever technology node you want; for example .5um from MOSIS is fairly affordable and used commonly in academic settings.

In HIP you would need the same technology that the HIP is delivered in. Since this will most likely be more advanced technologies, the cost will go up significantly. Masks in newer technologies run upwards of millions of dollars per mask, and you need around 20-30 masks for a 5-10 metal layer IC.

Overall the cost is going to be quite prohibitive unless you can line up buyers and you will most likely need a small team of engineers to properly design, validate, and manufacture this.

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First point to go to is Zilog, there're other organizations who have license for the core. What I got from interacting with them is that they may not be interested in the deal unless it will bring significant dividends for them. You should take it into account because before you even start to discuss numbers and deal in overall you should be able to convince them that your implementation is worth talking and thinking about.

Next, as I see from the comments to the question, you are going to make DSP device. Some DSP capabilities (e.g. ADC/DAC) may not be properly implemented in FPGA, thus FPGA has relatively limited application here, and you will need another entities (on the board or in silicon) providing these functionalities.

However even with multiple chip design it will be cheaper and will provide speed required for video DSP. For that you can use any modern FPGA, and select ADC/DAC carefully, and, what's most important, make proper board design which accounts for high digital speed.

If you need 32K buffer for your video processing - FPGAs are having such memories which can work @200 Mhz, should be enough for more or less sophisticated digital signal processing (given, again, you select RAM organization properly).

Finally, you can make your own implementation of Z80, without reference to the original design, only utilizing command set and operational structure, and even not accounting for native Z80 timing making you implementation running at much higher speed than 20 Mhz which is a maximum for Z80. It is not a hard work, but after you make such implementation you should be able to write microcode in Z80 assembler, which may be harder given capabilities of the debugging utilities which you design.

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