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I am working on my first Systems project as a student and I am learning how to integrate chips as I go along in Altium.

I recently came across this question in which you provided a rule for determining the solder mask expansion sizes for BGA Chips: What is the pad size required for this BGA AW H3 Chip?

I am wondering if there is a similar set of rules for QFN chips? We have a PMIC that we are integrating on Altium and we just want to make sure that our solder mask expansion sizes are sufficient. Currently we have the small pads having dimensions of 0.25x0.50mm and a solder mask expansion of 0.05mm.

Here's the link to the QFN Chip:

enter image description here

Also, we are drawing the footprints for the passives that we are going to use (0402,0603, 1005, etc.). Will it be okay to have the same footprint (with relaxed dimensions) for Capacitors, Resistors, and Inductors? What is an appropriate way to design the footprint for the passives?

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Use the IPC wizard to design the footprints from the device dimensions and tolerances. QFN and discretes are definitely covered, DFN may not be, at least in older versions.

You should take into account the registration and minimum solder mask sliver your PCB house can handle, but normally 75um and a 75um sliver is okay. 50um seems rather tight. For pitches finer than 500um (as with your 400um fine pitch chip) you may need to forgo the mask slivers between lands.

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